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1. 发明授权

US4680653A Rotating storage device track format emulation 失效
标题翻译：旋转存储设备轨道格式仿真
公开(公告)号：US4680653A
公开(公告)日：1987-07-14
申请号：US866632
申请日：1986-05-22
申请人： Chan Y. Ng , Norman K. Ouchi , David T. Wang , Wellington C. Yu
发明人： Chan Y. Ng , Norman K. Ouchi , David T. Wang , Wellington C. Yu
IPC分类号： G11B20/12 , G11B27/30 , G11B5/012
CPC分类号： G11B27/3027 , G11B20/1262 , G11B2020/1087 , G11B2020/10879 , G11B2020/1257
摘要： Disclosed is a method for recording a record that emulates a first recording format, which includes a track reference point, such as an index field, used for determining a position of a record on a track according to the first recording format, on a moving storage device operating according to a second recording format which also includes a track reference point. The invention comprises the steps, responsive to location information generated according to the first recording formats, of:(1) determining an original angular position of a record according to the first recording format;(2) calculating in response to the original angular position and a parameter a preferred angular position for the record according to the second recording format;(3) determining an actual angular position of the record recorded according to the second recording format; and(4) recording an extension of the record to compensate for the difference between the preferred angular position and the actual angular position.
摘要翻译：公开了一种用于记录模拟第一记录格式的记录的方法，其包括用于根据第一记录格式在轨道上确定记录的位置的诸如索引字段的轨道参考点在移动存储器设备根据还包括轨道参考点的第二记录格式进行操作。本发明包括响应于根据第一记录格式生成的位置信息的步骤：（1）根据第一记录格式确定记录的原始角位置; （2）响应于原始角位置计算和根据第二记录格式的用于记录的优选角位置的参数; （3）确定根据第二记录格式记录的记录的实际角位置; 和（4）记录记录的延伸部以补偿优选角位置与实际角位置之间的差。

2. 发明授权

US4745604A Method and apparatus for transferring data between a host processor and a data storage device 失效
标题翻译：用于在主处理器和数据存储设备之间传送数据的方法和装置
公开(公告)号：US4745604A
公开(公告)日：1988-05-17
申请号：US921022
申请日：1986-10-20
申请人： Arvind M. Patel , David T. Wang , Wellington C. Yu
发明人： Arvind M. Patel , David T. Wang , Wellington C. Yu
IPC分类号： G06F3/06 , G06F11/10 , G11B20/10 , G11B20/18 , H03M13/00 , H03M13/03
CPC分类号： G06F3/0601 , G06F11/10 , H03M13/03 , G06F2003/0692
摘要： In a data processing system in which two-level error correction is performed on variable length data being transferred between the host processor and the data storage device, the logical length of the data being transferred is computed during a fixed time gap with computation continuing after termination of the fixed time gap and commencement of the data transfer. The computation required for the logical length of the data field to accommodate two-level ECC is accomplished by first comparing the actual field length with a value predetermined by the subblock length of the two-level ECC. If the actual length is greater than the predetermined value, then a value equal to the subblock length plus first level ECC bytes is loaded into a counter which begins decrementing at the termination of the fixed time gap so as to synhronize by the byte-by-byte transfer of the data. As the data is being transferred the computation continues. When the computation has been completed, a value equal to the difference between the computed logical length and the subblock length plus first level ECC bytes is loaded into other counters which begin decrementing when the first counter reaches zero. In this manner transfer of the data is not interrupted. This permits two-level ECC to be incorporated into prior data processing systems which utilize a conventional track format with predetermined fixed time gaps, even though such fixed time gaps would otherwise be of insufficient duration to permit computation of the logical length required for two-level ECC.
摘要翻译：在对主机处理器和数据存储装置之间传送的可变长度数据进行二级纠错的数据处理系统中，在固定时间间隔内计算正在传输的数据的逻辑长度，并在终止后继续计算的固定时间间隔和数据传输的开始。通过首先将实际字段长度与由两级ECC的子块长度预定的值进行比较来实现数据字段的逻辑长度以适应两级ECC的计算所需的计算。如果实际长度大于预定值，则将等于子块长度加上第一级ECC字节的值加载到计数器中，该计数器在固定时间间隔的终止时开始递减，以逐个逐位地同步，字节传输数据。随着数据的传输，计算继续。当计算完成时，将等于计算的逻辑长度与子块长度加上第一级ECC字节之间的差的值加载到其他计数器中，当第一个计数器达到零时开始递减。以这种方式传输数据不会中断。这允许将两级ECC并入先前的数据处理系统，这些数据处理系统利用具有预定固定时间间隔的常规磁道格式，即使这样的固定时间间隙将不足以使计算两级所需的逻辑长度 ECC。

3. 发明授权

US09727458B2 Translating an address associated with a command communicated between a system and memory circuits 有权
公开(公告)号：US09727458B2
公开(公告)日：2017-08-08
申请号：US13620650
申请日：2012-09-14
申请人： David T. Wang , Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , Frederick Daniel Weber
发明人： David T. Wang , Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , Frederick Daniel Weber
IPC分类号： G06F13/00 , G06F12/02 , G06F13/42 , G06F13/28 , G11C11/406 , G11C11/4093
CPC分类号： G06F12/0292 , G06F13/28 , G06F13/4243 , G11C11/406 , G11C11/40618 , G11C11/4093 , Y02D10/14 , Y02D10/151
摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to translate an address associated with a command communicated between the system and the memory circuits.

4. 发明授权

US09542353B2 System and method for reducing command scheduling constraints of memory circuits 有权
标题翻译：用于减少存储器电路的命令调度约束的系统和方法
公开(公告)号：US09542353B2
公开(公告)日：2017-01-10
申请号：US11929225
申请日：2007-10-30
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F13/00 , G06F13/42 , G06F13/28 , G11C11/406 , G11C11/4093
CPC分类号： G06F13/4243 , G06F13/28 , G11C11/406 , G11C11/40618 , G11C11/4093 , Y02D10/14 , Y02D10/151
摘要： A memory circuit system and method are provided. An interface circuit is capable of communication with a plurality of memory circuits and a system. In use, the interface circuit is operable to interface the memory circuits and the system for reducing command scheduling constraints of the memory circuits.
摘要翻译：提供了一种存储器电路系统和方法。接口电路能够与多个存储器电路和系统通信。在使用中，接口电路可操作以连接存储器电路和系统，以减少存储器电路的命令调度约束。

5. 发明申请

US20140192583A1 CONFIGURABLE MEMORY CIRCUIT SYSTEM AND METHOD 有权
标题翻译：可配置存储器电路系统和方法
公开(公告)号：US20140192583A1
公开(公告)日：2014-07-10
申请号：US14090342
申请日：2013-11-26
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastien Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastien Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G11C5/06
CPC分类号： G11C5/06 , G06F13/1694 , G11C7/10 , G11C11/4063 , G11C29/44 , G11C29/808 , G11C2029/0409 , H01L2224/16145 , H01L2224/16225 , H01L2224/48091 , H01L2924/00014
摘要： A memory circuit system and method are provided in the context of various embodiments. In one embodiment, an interface circuit remains in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for performing various functionality (e.g. power management, simulation/emulation, etc.).
摘要翻译：在各种实施例的上下文中提供存储器电路系统和方法。在一个实施例中，接口电路保持与多个存储器电路和系统通信。接口电路可操作以将存储器电路和系统接口用于执行各种功能（例如电源管理，仿真/仿真等）。

6. 发明授权

US08710862B2 Programming of DIMM termination resistance values 有权
标题翻译：对DIMM终端电阻值进行编程
公开(公告)号：US08710862B2
公开(公告)日：2014-04-29
申请号：US13455691
申请日：2012-04-25
申请人： Philip Arnold Ferolito , Daniel L. Rosenband , David T. Wang , Michael John Smith
发明人： Philip Arnold Ferolito , Daniel L. Rosenband , David T. Wang , Michael John Smith
IPC分类号： H03K17/16 , H03K19/003 , G11C7/10 , G11C8/00 , G06F13/00 , G06F13/28
CPC分类号： G06F13/4086 , Y02D10/14 , Y02D10/151
摘要： Systems, methods, and apparatus, including computer program products, for providing termination resistance in a memory module are provided. An apparatus is provided that includes a plurality of memory circuits; an interface circuit operable to communicate with the plurality of memory circuits and to communicate with a memory controller; and a transmission line electrically coupling the interface circuit to a memory controller, wherein the interface circuit is operable to terminate the transmission line with a single termination resistance that is selected based on a plurality of resistance-setting commands received from the memory controller.
摘要翻译：提供了用于在存储器模块中提供终端电阻的系统，方法和装置，包括计算机程序产品。提供了一种包括多个存储电路的装置; 接口电路，其可操作以与所述多个存储器电路通信并与存储器控制器通信; 以及将接口电路电耦合到存储器控制器的传输线，其中所述接口电路可操作以基于从所述存储器控制器接收的多个电阻设置命令而选择的单个终端电阻终止所述传输线。

7. 发明授权

US08595419B2 Memory apparatus operable to perform a power-saving operation 有权
标题翻译：可操作以执行省电操作的存储装置
公开(公告)号：US08595419B2
公开(公告)日：2013-11-26
申请号：US13182234
申请日：2011-07-13
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F12/00
CPC分类号： G11C7/1072 , G06F13/4243 , G11C7/10 , G11C11/406 , G11C11/40618 , Y02D10/14 , Y02D10/151
摘要： A memory apparatus includes multiple memory circuits and an interface circuit to present to a host system emulated memory circuits. The interface circuit includes a first component of a first type and a second component of a second type, the first component and the second component being operable to present a host-system interface to the host system and to present a memory-circuit interface to the plurality of memory circuits, in which there is a difference in at least one aspect between the host-system interface and the memory circuit interface. At least one of the first and second components is operable to identify one or more memory circuits that is not being accessed and to perform a power-saving operation on the one or more memory circuits identified as not being accessed, where the power-saving operation includes placing the memory circuits identified as not being accessed in a precharge power down mode.
摘要翻译：存储装置包括多个存储器电路和用于向主机系统呈现仿真存储器电路的接口电路。接口电路包括第一类型的第一组件和第二类型的第二组件，第一组件和第二组件可操作以向主机系统呈现主机系统接口并向存储器电路接口呈现存储器电路接口多个存储器电路，其中在主机系统接口和存储器电路接口之间的至少一个方面存在差异。第一和第二组件中的至少一个可操作以识别未被访问的一个或多个存储器电路，并且对被识别为未访问的一个或多个存储器电路进行功率保存操作，其中省电操作包括将识别为未被访问的存储器电路放置在预充电掉电模式中。

8. 发明授权

US08280714B2 Memory circuit simulation system and method with refresh capabilities 有权
标题翻译：内存电路仿真系统及具备刷新能力的方法
公开(公告)号：US08280714B2
公开(公告)日：2012-10-02
申请号：US11553399
申请日：2006-10-26
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F17/50
CPC分类号： G11C11/406 , G11C7/10 , G11C11/40618
摘要： A system and method are provided including an interface circuit in communication with a plurality of memory circuits and a system. The interface circuit is operable to interface the plurality of memory circuits and the system for simulating at leas one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. The interface circuit is further operable to control refreshing of the plurality of memory circuits.
摘要翻译：提供了一种系统和方法，包括与多个存储器电路和系统通信的接口电路。所述接口电路可操作以使所述多个存储器电路和所述系统与至少一个不同于所述多个存储器电路中的至少一个的至少一个方面的至少一个存储器电路进行模拟。接口电路还可操作以控制多个存储器电路的刷新。

9. 发明授权

US08154935B2 Delaying a signal communicated from a system to at least one of a plurality of memory circuits 有权
标题翻译：将从系统传送的信号延迟到多个存储器电路中的至少一个
公开(公告)号：US08154935B2
公开(公告)日：2012-04-10
申请号：US12769428
申请日：2010-04-28
申请人： Suresh Natarajan Rajan , Keith R Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G11C11/00
CPC分类号： G11C8/18 , G11C5/04 , G11C7/1066 , G11C8/12 , G11C11/406 , G11C11/40618 , G11C29/50012
摘要： A system and method are provided for delaying a signal communicated from a system to a plurality of memory circuits. Included is a component in communication with a plurality of memory circuits and a system. Such component is operable to receive a signal from the system and communicate the signal to at least one of the memory circuits after a delay. In other embodiments, the component is operable to receive a signal from at least one of the memory circuits and communicate the signal to the system after a delay.
摘要翻译：提供了一种用于将从系统传送的信号延迟到多个存储器电路的系统和方法。包括与多个存储器电路和系统通信的部件。这样的组件可操作以从系统接收信号并且在延迟之后将该信号传送到至少一个存储器电路。在其他实施例中，组件可操作以从至少一个存储器电路接收信号，并在延迟之后将该信号传送到系统。

10. 发明授权

US08112266B2 Apparatus for simulating an aspect of a memory circuit 有权
标题翻译：用于模拟存储器电路的一个方面的装置
公开(公告)号：US08112266B2
公开(公告)日：2012-02-07
申请号：US11929500
申请日：2007-10-30
申请人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
发明人： Suresh Natarajan Rajan , Keith R. Schakel , Michael John Sebastian Smith , David T. Wang , Frederick Daniel Weber
IPC分类号： G06F9/455
CPC分类号： G06F17/5009 , G06F2217/84 , G11C7/10 , G11C11/406 , G11C11/40618
摘要： A memory subsystem is provided including an interface circuit adapted for coupling with a plurality of memory circuits and a system. The interface circuit is operable to interface the memory circuits and the system for emulating at least one memory circuit with at least one aspect that is different from at least one aspect of at least one of the plurality of memory circuits. Such aspect includes a signal, a capacity, a timing, and/or a logical interface.
摘要翻译：提供存储器子系统，其包括适于与多个存储器电路和系统耦合的接口电路。接口电路可操作以使存储器电路和系统接口，用于仿真至少一个与至少一个存储器电路的至少一个方面不同的方面的存储器电路。这种方面包括信号，容量，定时和/或逻辑接口。

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