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    • 6. 发明授权
    • Systems and methods for access violation management of secured memory
    • 安全内存访问违规管理的系统和方法
    • US07836269B2
    • 2010-11-16
    • US11618075
    • 2006-12-29
    • Willy ObereinerVenkat NatarajanJeremy Isaac Nathaniel WernerJoe Yuen TomHyun Soo Lee
    • Willy ObereinerVenkat NatarajanJeremy Isaac Nathaniel WernerJoe Yuen TomHyun Soo Lee
    • G06F13/16
    • G06F12/1483G06F21/53
    • Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.
    • 便于处理数据并保护写入或读取内存的数据的系统和方法。 处理器可以包括主机存储器接口,其监视主处理器和存储器之间的所有总线流量。 主机存储器接口可以分析主机处理器产生的命令,并确定命令的有效性。 有效的命令可以进行进一步分析; 无效命令可以被中止,例如,主机存储器接口和存储器都设置为空闲状态。 主机存储器接口可以分析通过认证组件获得的认证信息和关于存储器分区权限的信息,以确定是否存在关于该命令的命令分区违例。 如果存在违规,则主机存储器接口可以防止不正确的命令在存储器中执行,并且可能导致不同的操作发生,从而允许将存储器置于已知状态。
    • 9. 发明授权
    • Circuit for and method of processing data input to a first-in first-out memory
    • 用于处理输入到先进先出存储器的数据的电路和方法
    • US07620752B1
    • 2009-11-17
    • US11218410
    • 2005-09-01
    • Hyun Soo Lee
    • Hyun Soo Lee
    • G06F3/00
    • G06F13/4059
    • A method of processing data input to a first-in first-out memory is disclosed. The method comprises steps of receiving input data words from a pipeline stage at an input of the first-in first-out memory; receiving data valid bits associated with the pipeline stage; generating a count associated with the data valid bits; and coupling the count to the first-in first-out memory. The step of generating a count associated with the data valid bits may comprise encoding the data valid bits to generate a valid data word representing the number of pipeline stages having valid data. The method of further comprises a step of generating an almost full signal based upon the count, and in particular generating an almost full signal when a read pointer incremented by the count of valid bits in the pipeline stages equals a write pointer. A circuit for processing data is also disclosed.
    • 公开了一种处理输入到先进先出存储器的数据的方法。 该方法包括以下步骤:在先入先出存储器的输入处从流水线级接收输入数据字; 接收与流水线级相关联的数据有效位; 生成与数据有效位相关联的计数; 并将计数耦合到先进先出存储器。 产生与数据有效位相关联的计数的步骤可以包括对数据有效位进行编码,以生成表示具有有效数据的流水线级数的有效数据字。 所述方法还包括基于所述计数产生几乎全信号的步骤,并且特别是当通过所述流水线级中的有效位的计数增加的读指针等于写指针时,产生几乎全信号。 还公开了一种用于处理数据的电路。
    • 10. 发明申请
    • SYSTEMS AND METHODS FOR ACCESS VIOLATION MANAGEMENT OF SECURED MEMORY
    • 安全存储器访问管理的系统和方法
    • US20080162784A1
    • 2008-07-03
    • US11618075
    • 2006-12-29
    • Willy ObereinerVenkat NatarajanJeremy Isaac Nathaniel WernerJoe Yuen TomHyun Soo Lee
    • Willy ObereinerVenkat NatarajanJeremy Isaac Nathaniel WernerJoe Yuen TomHyun Soo Lee
    • G06F12/14G06F12/02
    • G06F12/1483G06F21/53
    • Systems and methods that facilitate processing data and securing data written to or read from memory. A processor can include a host memory interface that monitors all bus traffic between a host processor and memory. The host memory interface can analyze commands generated by the host processor and determine the validity of the commands. Valid commands can proceed for further analysis; invalid commands can be aborted, for example, with the host memory interface and memory each set to an idle state. The host memory interface can analyze authentication information obtained via an authentication component, and information regarding memory partition rights, to determine whether a command partition violation exists as to the command. If a violation exists, the host memory interface can prevent the improper command from executing in the memory, and can cause a different operation to occur thereby allowing the memory to be placed in a known state.
    • 便于处理数据并保护写入或读取内存的数据的系统和方法。 处理器可以包括主机存储器接口,其监视主处理器和存储器之间的所有总线流量。 主机存储器接口可以分析主机处理器产生的命令,并确定命令的有效性。 有效的命令可以进行进一步分析; 无效命令可以被中止,例如,主机存储器接口和存储器都设置为空闲状态。 主机存储器接口可以分析通过认证组件获得的认证信息和关于存储器分区权限的信息,以确定是否存在关于该命令的命令分区违例。 如果存在违规,则主机存储器接口可以防止不正确的命令在存储器中执行,并且可能导致不同的操作发生,从而允许将存储器置于已知状态。