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1. 发明授权

US06649466B2 Method of forming DRAM circuitry 失效
标题翻译：形成DRAM电路的方法
公开(公告)号：US06649466B2
公开(公告)日：2003-11-18
申请号：US10243385
申请日：2002-09-13
申请人： Cem Basceri , Garo J. Derderian , M. R. Visokay , J. M. Drynan , Gurtej S. Sandhu
发明人： Cem Basceri , Garo J. Derderian , M. R. Visokay , J. M. Drynan , Gurtej S. Sandhu
IPC分类号： H01L218242
CPC分类号： H01L21/31122 , H01L21/28061 , H01L21/28518 , H01L21/28556 , H01L21/28568 , H01L21/31604 , H01L21/32051 , H01L27/10811 , H01L27/10888 , H01L28/90 , H01L29/6659
摘要： In part, disclosed are semiconductor processing methods, methods of depositing a tungsten comprising layer over a substrate, methods of depositing a tungsten nitride comprising layer over a substrate, methods of depositing a tungsten silicide comprising layer over a substrate, methods of forming a transistor gate line over a substrate, methods of forming a patterned substantially crystalline Ta2O5 comprising material, and methods of forming a capacitor dielectric region comprising substantially crystalline Ta2O5 comprising material. In one implementation, a semiconductor processing method includes forming a substantially amorphous Ta2O5 comprising layer over a semiconductive substrate. The layer is exposed to WF6 under conditions effective to etch substantially amorphous Ta2O5 from the substrate. In one implementation, the layer is exposed to WF6 under conditions effective to both etch substantially amorphous Ta2O5 from the substrate and deposit a tungsten comprising layer over the substrate during the exposing.
摘要翻译：部分地，公开了半导体处理方法，在衬底上沉积含钨层的方法，在衬底上沉积含氮化钨的层的方法，在衬底上沉积包含硅化钨的层的方法，形成晶体管栅极的方法在衬底上划线，形成图案化的基本上结晶的Ta 2 O 5的材料的方法，以及形成包含基本上结晶的Ta 2 O 5的材料的电容器电介质区域的方法。在一个实施方案中，半导体处理方法包括在半导体衬底上形成包含基本非晶态的Ta 2 O 5层。该层在有效从底物上蚀刻基本无定形Ta 2 O 5的条件下暴露于WF6。在一个实施方案中，该层在有效地从衬底上蚀刻基本上无定形Ta 2 O 5的条件下暴露于WF6，并在曝光期间在衬底上沉积含钨层。

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