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1. 发明授权

US5039939A Calculating AC chip performance using the LSSD scan path 失效
标题翻译：使用LSSD扫描路径计算交流芯片性能
公开(公告)号：US5039939A
公开(公告)日：1991-08-13
申请号：US291919
申请日：1988-12-29
申请人： Carroll J. Dick , Bruce J. Ditmyer , Thomas L. Jeremiah , Lawrence Jones , Gregory S. Still
发明人： Carroll J. Dick , Bruce J. Ditmyer , Thomas L. Jeremiah , Lawrence Jones , Gregory S. Still
IPC分类号： G01R31/28 , G01R31/3185 , H01L21/66
CPC分类号： G01R31/31858
摘要： Chip performance is measured using LSSD logic to propagate a signal through the LSSD scan path of the chip. The measurement data is compared to tabular data which is used to classify the AC chip performance. The use of the LSSD scan path provides an accurate overall measurement of an entire chip. The circuitry is internal to the system and does not require external test circuitry. No unique test patterns are required for a given chip design. The chip measurements can be made after installation of the chip in a field operational environment as well as during a manufacturing and testing environment. The chip measurements can be made by local execution of the testing or controlled from a remote location.

2. 发明授权

US08521982B2 Load request scheduling in a cache hierarchy 有权
标题翻译：在缓存层次结构中加载请求调度
公开(公告)号：US08521982B2
公开(公告)日：2013-08-27
申请号：US12424207
申请日：2009-04-15
申请人： Robert A. Cargnoni , Guy L. Guthrie , Thomas L. Jeremiah , Stephen J. Powell , William J. Starke , Jeffrey A. Steucheli
发明人： Robert A. Cargnoni , Guy L. Guthrie , Thomas L. Jeremiah , Stephen J. Powell , William J. Starke , Jeffrey A. Steucheli
IPC分类号： G06F12/00
CPC分类号： G06F12/123 , G06F12/084 , G06F12/0897
摘要： A system and method for tracking core load requests and providing arbitration and ordering of requests. When a core interface unit (CIU) receives a load operation from the processor core, a new entry in allocated in a queue of the CIU. In response to allocating the new entry in the queue, the CIU detects contention between the load request and another memory access request. In response to detecting contention, the load request may be suspended until the contention is resolved. Received load requests may be stored in the queue and tracked using a least recently used (LRU) mechanism. The load request may then be processed when the load request resides in a least recently used entry in the load request queue. CIU may also suspend issuing an instruction unless a read claim (RC) machine is available. In another embodiment, CIU may issue stored load requests in a specific priority order.
摘要翻译：用于跟踪核心负载请求并提供仲裁和请求排序的系统和方法。当核心接口单元（CIU）从处理器核心接收到加载操作时，分配在CIU队列中的新条目。响应于在队列中分配新条目，CIU检测加载请求和另一个存储器访问请求之间的争用。响应于检测到争用，负载请求可以被暂停，直到争用被解决。接收到的加载请求可以存储在队列中，并使用最近最少使用的（LRU）机制进行跟踪。然后可以在加载请求驻留在加载请求队列中最近最少使用的条目中时处理加载请求。除非读取权利要求（RC）机器可用，否则CIU也可以暂停发出指令。在另一个实施例中，CIU可以以特定优先级顺序发布存储的加载请求。

3. 发明申请

US20100262784A1 Empirically Based Dynamic Control of Acceptance of Victim Cache Lateral Castouts 有权
标题翻译：基于经验的动态控制接受受害者缓存横向铸件
公开(公告)号：US20100262784A1
公开(公告)日：2010-10-14
申请号：US12421017
申请日：2009-04-09
申请人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
发明人： Guy L. Guthrie , Harmony L. Helterhoff , Thomas L. Jeremiah , Alvan W. Ng , William J. Starke , Jeffrey A. Stuecheli , Philip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/126 , G06F12/0811 , G06F12/0815 , G06F12/0862
摘要： A second lower level cache receives an LCO command issued by a first lower level cache on an interconnect fabric. The LCO command indicates an address of a victim cache line to be castout from the first lower level cache and indicates that the second lower level cache is an intended destination of the victim cache line. The second lower level cache determines whether to accept the victim cache line from the first lower level cache based at least in part on the address of the victim cache line indicated by the LCO command. In response to determining not to accept the victim cache line, the second lower level cache provides a coherence response to the LCO command refusing the identified victim cache line. In response to determining to accept the victim cache line, the second lower level cache updates an entry corresponding to the identified victim cache line.
摘要翻译：第二低级缓存接收由互连结构上的第一较低级缓存发出的LCO命令。 LCO命令指示要从第一较低级高速缓存丢弃的受害者高速缓存行的地址，并且指示第二较低级高速缓存是受害者高速缓存行的预期目的地。第二较低级缓存至少部分地基于由LCO命令指示的受害缓存行的地址来确定是否从第一低级缓存接受受害者高速缓存行。响应于确定不接受受害者缓存行，第二较低级缓存为LCO命令提供拒绝所识别的受害者缓存行的一致性响应。响应于确定接受受害者缓存行，第二较低级缓存更新对应于所识别的受害者高速缓存行的条目。

4. 发明申请

US20100100682A1 Victim Cache Replacement 有权
标题翻译：受害者缓存替换
公开(公告)号：US20100100682A1
公开(公告)日：2010-04-22
申请号：US12256002
申请日：2008-10-22
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0811 , G06F12/0831 , G06F12/0862 , G06F12/128 , G06F2212/1028 , Y02D10/13
摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core that specifies a non-modifying access to a target coherency granule, a determination is made whether the memory access request hits or misses in a directory of the lower level victim cache. In response to determining that the memory access request hits in the lower level victim cache in a data-valid coherence state, the lower level victim cache provides the target coherency granule of the memory access request to the upper level cache. The lower level victim cache preserves the target coherency granule in the lower level victim cache in a shared coherence state if the memory access request is of a first type and invalidates the target coherency granule if the memory access request is of a second type.
摘要翻译：数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。响应于指定对目标一致性粒子的不修改访问的处理器核心的存储器访问请求，确定存储器访问请求是否在较低级别的受害缓存的目录中命中或丢失。响应于确定存储器访问请求在数据有效的相干状态中击中较低级别的受害者高速缓存，则较低级别的受害者缓存将存储器访问请求的目标一致性颗粒提供给高级缓存。如果存储器访问请求是第一类型，则较低级别的受害者缓存在共享相干状态下保留较低级别的受害者缓存中的目标一致性粒子，如果存储器访问请求是第二类型，则使目标一致性粒子无效。

5. 发明授权

US5446850A Cross-cache-line compounding algorithm for scism processors 失效
标题翻译： Scic处理器的跨缓存行复合算法
公开(公告)号：US5446850A
公开(公告)日：1995-08-29
申请号：US281321
申请日：1994-07-27
申请人： Thomas L. Jeremiah , Bartholomew Blaner
发明人： Thomas L. Jeremiah , Bartholomew Blaner
IPC分类号： G06F9/38 , G06F12/08
CPC分类号： G06F9/382 , G06F9/3802 , G06F9/3808 , G06F9/3812 , G06F9/3816 , G06F9/3842 , G06F9/3853
摘要： A system for compounding instructions across cache line boundaries transfers an instruction line from a relatively slow memory to a instruction compounding unit if there is a miss for an instruction in that line in the instruction cache. At the same time the numerically preceding instruction in cache is transferred to the instruction compounding unit and instructions from the two lines are compounded. If a numerically preceding cache line has been compounded with a cache line that has been deleted and then replaced, compounding tags for the numerically preceding cache line are deleted.
摘要翻译：如果在指令高速缓存中的该行中的指令存在缺失，则用于在高速缓存行边界之间复合指令的系统将指令行从相对较慢的存储器传送到指令复合单元。同时，高速缓存中的数字前面的指令被传送到指令复合单元，并且来自两行的指令复合。如果数字前面的高速缓存行与已经被删除然后被替换的高速缓存行复合，则删除数字前面的高速缓存行的复合标记。

6. 发明授权

US4234955A Parity for computer system having an array of external registers 失效
标题翻译：具有外部寄存器阵列的计算机系统的奇偶校验
公开(公告)号：US4234955A
公开(公告)日：1980-11-18
申请号：US6712
申请日：1979-01-26
申请人： Thomas L. Jeremiah , Karl F. Pezdirtz
发明人： Thomas L. Jeremiah , Karl F. Pezdirtz
IPC分类号： G06F11/10
CPC分类号： G06F11/1008 , G06F11/1076
摘要： For a computer system having an array of external registers which may be used as a data source or data destination, wherein such system uses an odd parity checking system, and wherein certain of the register position in the external array can be vacant, an improved parity checking configuration includes a plurality of parity bit latches, one for each location in the external register array. The parity bit latches are set by an initial microprogram load to provide an odd parity bit for each location in the external array of registers which is empty or which may be faulty, disabled or malfunctioning. This assures that when the external array is searched by row, that all of the array locations will provide the appropriate parity check regardless of whether a byte of information exists therein or not.
摘要翻译：对于具有可用作数据源或数据目的地的外部寄存器阵列的计算机系统，其中这种系统使用奇校验系统，并且其中外部阵列中的某些寄存器位置可以是空的，改进的奇偶校验检查配置包括多个奇偶校验位锁存器，一个用于外部寄存器阵列中的每个位置。奇偶校验位锁存器由初始微程序负载设置，为外部寄存器阵列中的每个位置提供奇偶校验位，该寄存器为空或可能有故障，禁用或故障。这确保当外部阵列被行搜索时，所有的阵列位置都将提供适当的奇偶校验，而不管其中是否存在一个字节的信息。

7. 发明申请

US20100023695A1 Victim Cache Replacement 有权
标题翻译：受害者缓存替换
公开(公告)号：US20100023695A1
公开(公告)日：2010-01-28
申请号：US12177912
申请日：2008-07-23
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William J. Starke , Phillip G. Williams
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William J. Starke , Phillip G. Williams
IPC分类号： G06F12/08
CPC分类号： G06F12/0897 , G06F12/0817 , G06F12/127
摘要： A data processing system includes a processor core having an associated upper level cache and a lower level victim cache. In response to a memory access request of the processor core, the lower level cache victim determines whether the memory access request hits or misses in the directory of the lower level victim cache, and the upper level cache determines whether a castout from the upper level cache is to be performed and selects a victim coherency granule for eviction from the upper level cache. In response to determining that a castout from the upper level cache is to be performed, the upper level cache evicts the selected victim coherency granule. In the eviction, the upper level cache reads out the victim coherency granule from the data array of the upper level cache only in response to an indication that the memory access request misses in the directory of the lower level victim cache.
摘要翻译：数据处理系统包括具有相关联的高级缓存和较低级别的受害缓存的处理器核心。响应于处理器核心的存储器访问请求，下级缓存受害者确定存储器访问请求是否在较低级别的受害者高速缓存的目录中命中或丢失，并且上级缓存确定来自上级缓存的丢弃将被执行，并从上级缓存中选择被驱逐的受害者一致性粒子。响应于确定要执行来自上级高速缓存的停顿，上级高速缓存驱逐所选择的受害者一致性粒子。在逐出时，高级缓存器只有在响应于存储器访问请求在较低级别的受害者缓存的目录中丢失的指示时才从高级缓存的数据阵列读出受害者一致性粒子。

8. 发明授权

US5504932A System for executing scalar instructions in parallel based on control bits appended by compounding decoder 失效
标题翻译：基于由复合解码器附加的控制位并行执行标量指令的系统
公开(公告)号：US5504932A
公开(公告)日：1996-04-02
申请号：US488464
申请日：1995-06-07
申请人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
发明人： Stamatis Vassiliadis , Bartholomew Blaner , Thomas L. Jeremiah
IPC分类号： G06F9/30 , G06F9/318 , G06F9/38
CPC分类号： G06F9/382 , G06F9/30149 , G06F9/3017 , G06F9/3808 , G06F9/3812 , G06F9/3853 , G06F9/3885
摘要： An instruction processor system for decoding compound instructions created from a series of base instructions of a scalar machine, the processor generating a series of compound instructions with an instruction format text having appended control bits in the instruction format text enabling the execution of the compound instruction format text in said instruction processor with a compounding facility which fetches and decodes compound instructions which can be executed as compounded and single instructions by the arithmetic and logic units of the instruction processor while preserving intact the scalar execution of the base instructions of a scalar machine which were originally in storage. The system nullifies any execution of a member instruction unit of a compound instruction upon occurrence of possible conditions, such as branch, which would affect the correctness of recording results of execution of the member instruction unit portion based upon the interrelationship of member units of the compound instruction with other instructions. The resultant series of compounded instructions generally executes in a faster manner than the original format which is preserved due to the parallel nature of the compounded instruction stream which is executed.
摘要翻译：一种指令处理器系统，用于对由标量机的一系列基本指令产生的复合指令进行解码，该处理器产生具有指令格式文本的指令格式文本的一系列复合指令，该指令格式文本具有能够执行复合指令格式的指令格式文本中的附加控制位所述指令处理器中的文本具有复合设备，该复合设备提取和解码可由指令处理器的算术和逻辑单元作为复合指令和单个指令执行的复合指令，同时完整地保持标量机的基本指令的标量执行，最初在存储。该系统在发生可能的条件（例如分支）时，使复合指令的成员指令单元的任何执行无效，这将基于化合物的成员单元的相互关系而影响成员指令单元部分执行的记录结果的正确性指令与其他指令。所得到的一系列复合指令通常比由被执行的复合指令流的并行特性而保留的原始格式更快地执行。

9. 发明授权

US5386531A Computer system accelerator for multi-word cross-boundary storage access 失效
标题翻译：用于多字跨境存储访问的计算机系统加速器
公开(公告)号：US5386531A
公开(公告)日：1995-01-31
申请号：US700732
申请日：1991-05-15
申请人： Bartholomew Blaner , Raymond J. Eberhard , Thomas L. Jeremiah , Michael J. Mack
发明人： Bartholomew Blaner , Raymond J. Eberhard , Thomas L. Jeremiah , Michael J. Mack
IPC分类号： G06F9/312 , G06F9/38 , G06F12/04 , G06F12/06
CPC分类号： G06F9/3824 , G06F12/04 , G06F9/30043 , G06F9/3816
摘要： An instruction processing unit (IPU) and a storage array, a storage-to-instruction-processing-unit interface, including a hardware accelerator for cross-boundary storage access with a cross-boundary buffer for providing residual read and write data in support of high speed block concurrent accessing of multi-word operands of a computer system. A cross-boundary buffer (CBB) is used, coupled to a write rotating shifter, a write merger (WMERGE) and a write merge controller (WMCTL) which is coupled for an input to said control register (CREG) for sequencing data transmitted on the data bus for merger with data contained in the cross-boundary buffer (CBB) by the write merger before it is latched in a data bus out register, and for simultaneously also latching the data in the cross-boundary buffer (CBB), and for writing data from the data bus out register into the storage array in the next clock cycle of the instruction processor at the doubleword address addressed. The cross-boundary buffer (CCB) is also coupled to a read rotating shifter (RROTATE), a read merger (RMERGE) and a read merge controller which responds to control instruction sequencing. The storage-to-instruction-processing-unit interface operates on multiple words, with residues from a second and subsequent accesses allowing continuation of the accessing process beyond two memory words. The hardware can repeat a second microword until an operand of arbitrary length is transferred. The interface permits efficient data transfer to be interrupted and resumed at a desired point, for efficient execution of Load Multiple and Store Multiple operations.
摘要翻译：指令处理单元（IPU）和存储阵列，存储指令处理单元接口，包括用于跨边界存储访问的硬件加速器，用于提供冗余的读和写数据，以支持高速块并发访问计算机系统的多字操作数。使用跨边界缓冲器（CBB），耦合到写入旋转移位器，写入合并器（WMERGE）和写入合并控制器（WMCTL），写入合并控制器（WMCTL）被耦合到所述控制寄存器（CREG）的输入端，数据总线，用于与写入合并之前的数据总线输出寄存器锁存在跨界缓冲器（CBB）中的数据合并，同时还将数据锁存在跨边界缓冲器（CBB）中;以及用于将数据总线输出寄存器的数据写入指令处理器的下一个时钟周期，并以寻址的双字地址写入存储阵列。跨边界缓冲器（CCB）还耦合到读取旋转移位器（RROTATE），读取合并（RMERGE）和读取合并控制器，其响应于控制指令排序。存储到指令处理单元接口以多个字操作，具有来自第二和随后访问的残留，允许超过两个存储字的持续访问过程。硬件可以重复第二个微字直到任意长度的操作数被传送。该接口允许有效的数据传输被中断并在所需的时间点恢复，以便有效执行“加载多重”和“存储多个”操作。

10. 发明授权

US08117397B2 Victim cache line selection 有权
标题翻译：受害者缓存行选择
公开(公告)号：US08117397B2
公开(公告)日：2012-02-14
申请号：US12335809
申请日：2008-12-16
申请人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
发明人： Guy L. Guthrie , Thomas L. Jeremiah , William L. McNeil , Piyush C. Patel , William J. Starke , Jeffrey A. Stuecheli
IPC分类号： G06F12/00
CPC分类号： G06F12/126 , G06F12/0817 , G06F12/0862 , G06F12/0897 , Y02D10/13
摘要： A cache memory includes a cache array including a plurality of congruence classes each containing a plurality of cache lines, where each cache line belongs to one of multiple classes which include at least a first class and a second class. The cache memory also includes a cache directory of the cache array that indicates class membership. The cache memory further includes a cache controller that selects a victim cache line for eviction from a congruence class. If the congruence class contains a cache line belonging to the second class, the cache controller preferentially selects as the victim cache line a cache line of the congruence class belonging to the second class based upon access order. If the congruence class contains no cache line belonging to the second class, the cache controller selects as the victim cache line a cache line belonging to the first class based upon access order.
摘要翻译：高速缓存存储器包括包含多个等同类的高速缓存阵列，每个级别包含多条高速缓存行，其中每条高速缓存行属于至少包括第一类和第二类的多个类中的一个。缓存存储器还包括指示类成员资格的高速缓存阵列的高速缓存目录。高速缓冲存储器还包括高速缓存控制器，其选择用于从同余类驱逐的受害缓存行。如果同余类包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序优先选择属于第二类的同余类的高速缓存行作为受害缓存行。如果同余类不包含属于第二类的高速缓存行，则高速缓存控制器基于访问顺序选择属于第一类的高速缓存行作为受害缓存行。

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