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1. 发明授权

US5513133A Compact microelectronic device for performing modular multiplication and exponentiation over large numbers 失效
标题翻译：紧凑的微电子器件，用于大量执行模乘和求幂
公开(公告)号：US5513133A
公开(公告)日：1996-04-30
申请号：US154220
申请日：1993-11-18
申请人： Carmi D. Cressel , David Hendel , Itai Dror , Isaac Hadad , Benjamin Arazi
发明人： Carmi D. Cressel , David Hendel , Itai Dror , Isaac Hadad , Benjamin Arazi
IPC分类号： G06F9/52 , G06F7/72 , G06F15/177 , G09C1/00 , G06F7/52 , G06F7/38
CPC分类号： G06F7/728
摘要： A compact synchronous microelectronic peripheral machine for standard microprocessors with means for proper clocking and control, has as essential elements: three main subdivided, switched and docked shift registers, B, S, and N; two only multiplexed serial/parallel multipliers; borrow detectors, ancillary subtractors and adders; delay registers and switching elements; all of which embody a totally integrated concurrent and synchronous process approach to modular multiplication, squaring, and exponentiation. A method for carrying out modular multiplication, wherein the multiplicand A , the multiplier B and the modul, N, comprise m characters of k bits each, the multiplier not being greater than the modulus, is also described, wherein the multiplicand can be much larger than the modulus. It is demonstrated how the device can be used as a large number processor in the normal field of numbers.
摘要翻译：具有正确时钟和控制功能的标准微处理器的紧凑型同步微电子外围设备具有以下基本要素：三个主要细分，开关和对接移位寄存器B，S和N; 两个仅复用的串行/并行乘法器; 借用检测器，辅助减法器和加法器; 延迟寄存器和开关元件; 所有这些都体现了一种完全集成的并行和同步过程方法来进行模乘，平方和求幂。一种用于执行模乘法的方法，其中被乘数A，乘法器B和调制N包括k位的m个字符，乘法器不大于模数，其中被乘数可以大得多比模数。演示了如何将该设备用作正常数字领域中的大量处理器。

2. 发明授权

US5742530A Compact microelectronic device for performing modular multiplication and exponentiation over large numbers 失效
标题翻译：紧凑的微电子器件，用于大量执行模乘和求幂
公开(公告)号：US5742530A
公开(公告)日：1998-04-21
申请号：US579951
申请日：1995-12-28
申请人： Carmi David Gressel , David Hendel , Itai Dror , Isaac Hadad , Benjamin Arazi
发明人： Carmi David Gressel , David Hendel , Itai Dror , Isaac Hadad , Benjamin Arazi
IPC分类号： G06F9/52 , G06F7/72 , G06F15/177 , G09C1/00 , G06F7/38
CPC分类号： G06F7/728
摘要： A compact synchronous microelectronic peripheral machine for standard microprocessors with means for proper clocking and control, has as essential elements: three main subdivided, switched and clocked shift registers, B, S, and N; two only multiplexed serial/parallel multipliers; borrow detectors, ancillary subtractors and adders; delay registers and switching elements; all of which embody a totally integrated concurrent and synchronous process approach to modular multiplication, squaring, and exponentiation. A method for carrying out modular multiplication, wherein the multiplicand A, the multiplier B and the modul, N, comprise m characters of k bits each, the multiplier not being greater than the modulus, is also described, wherein the multiplicand can be much larger than the modulus. It is demonstrated how the device can be used as a large number processor in the normal field of numbers.
摘要翻译：具有正确时钟和控制功能的标准微处理器的紧凑型同步微电子外围设备具有以下要素：三个主要细分，开关和时钟移位寄存器B，S和N; 两个仅复用的串行/并行乘法器; 借用检测器，辅助减法器和加法器; 延迟寄存器和开关元件; 所有这些都体现了一种完全集成的并行和同步过程方法来进行模乘，平方和求幂。一种用于执行模乘法的方法，其中被乘数A，乘法器B和调制N包括k位的m个字符，乘法器不大于模数，其中被乘数可以大得多比模数。演示了如何将该设备用作正常数字领域中的大量处理器。

3. 发明授权

US06185596B2 Apparatus & method for modular multiplication & exponentiation based on Montgomery multiplication 失效
标题翻译：基于蒙哥马利乘法的乘法和乘法的装置与方法
公开(公告)号：US06185596B2
公开(公告)日：2001-02-06
申请号：US09050958
申请日：1998-04-01
申请人： Isaac Hadad , Benjamin Arazi , Carmi David Gressel , Itai Dror
发明人： Isaac Hadad , Benjamin Arazi , Carmi David Gressel , Itai Dror
IPC分类号： G06F738
CPC分类号： G06F7/728
摘要： A modular arithmetic method and microelectronic apparatus therefore, operative to perform a sequence of interleaved Montgomery type multiplications and squaring operations, involves performing a sequence of modular multiplications and squarings using only a single carry save adder. Each multiplication is operative to perform the equivalent of three natural integer multiplication operations using an anticipatory device to determine a Y0 value, such that a result is an exponentiation.
摘要翻译：因此，可操作以执行交错蒙哥马利类型乘法和平方运算序列的模运算方法和微电子装置涉及仅使用单个进位保存加法器来执行一系列模乘法和方法。每个乘法可操作以使用预期设备来执行三次自然整数乘法运算的等价物来确定Y0值，使得结果是乘幂。

4. 发明授权

US06748410B1 Apparatus and method for modular multiplication and exponentiation based on montgomery multiplication 有权
标题翻译：基于montgomery乘法的乘法和乘法的装置和方法
公开(公告)号：US06748410B1
公开(公告)日：2004-06-08
申请号：US09480102
申请日：2000-01-10
申请人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
发明人： Carmi David Gressel , Isaac Hadad , Itai Dror , Alexey Molchanov , Michael Mostovoy
IPC分类号： G06F738
CPC分类号： G06F7/728
摘要： This invention discloses apparatus and methods for accelerating processing, loading and unloading of data, from and to a plurality of memory addresses in a CPU having an accumulator, and to a memory-mapped coprocessing device for continuous integer computations.
摘要翻译：本发明公开了一种用于加速处理，加载和卸载数据的装置和方法，该装置和方法来自具有累加器的CPU中的多个存储器地址，以及用于连续整数计算的存储器映射协处理装置。

5. 发明授权

US09246511B2 Method and apparatus to process data based upon estimated compressibility of the data 有权
标题翻译：基于估计的数据压缩性来处理数据的方法和装置
公开(公告)号：US09246511B2
公开(公告)日：2016-01-26
申请号：US13425016
申请日：2012-03-20
申请人： Alon Kipnis , Itai Dror
发明人： Alon Kipnis , Itai Dror
IPC分类号： G06F3/00 , H03M7/30 , H04L29/06
CPC分类号： H03M7/30 , H03M7/3071 , H03M7/3079 , H04L69/04
摘要： A method includes, in a data storage device, determining an estimated compression ratio. The estimated compression ratio is based on hash values of a subset of a data set. The method includes selectively processing the data set based on the estimated compression ratio prior to storage of data associated with the data set in a memory of the data storage device.
摘要翻译：一种方法包括在数据存储装置中确定估计的压缩比。估计压缩比基于数据集的子集的哈希值。该方法包括在存储与数据存储设备的存储器中的数据集相关联的数据之前，基于估计的压缩比来选择性地处理数据集。

6. 发明授权

US08744073B2 Digital random number generator based on digitally-controlled oscillators 失效
标题翻译：基于数字控制振荡器的数字随机数发生器
公开(公告)号：US08744073B2
公开(公告)日：2014-06-03
申请号：US13203690
申请日：2009-02-25
申请人： Itai Dror , Leonid Minz , Boris Dolgunov , Michael Koun
发明人： Itai Dror , Leonid Minz , Boris Dolgunov , Michael Koun
IPC分类号： H03K3/03
CPC分类号： G06F7/588
摘要： A system for random number generation includes a digital oscillator circuit, which has a set of available configurations and is operative to generate a random number sequence in accordance with a current configuration selected from the set. The system further includes a randomization circuit, which is operative to produce a pseudo-random stream of values corresponding to the available configurations of the digital oscillator circuit, and to control the digital oscillator circuit to alternate among the available configurations in accordance with the pseudo-random stream of values.
摘要翻译：用于随机数生成的系统包括数字振荡器电路，其具有一组可用配置，并且可操作以根据从组中选择的当前配置来生成随机数序列。该系统还包括随机化电路，其可操作地产生对应于数字振荡器电路的可用配置的值的伪随机流，并且根据伪随机电路控制数字振荡器电路在可用配置之间交替，随机流的值。

7. 发明授权

US08533558B2 System and method of error correction of control data at a memory device 有权
标题翻译：存储器件中控制数据的纠错系统和方法
公开(公告)号：US08533558B2
公开(公告)日：2013-09-10
申请号：US12955174
申请日：2010-11-29
申请人： Damian Pablo Yurzola , Rajeev Nagabhirava , Arjun Kapoor , Itai Dror , Annie Chi-San Chang , Peter Hwang , Jian Chen
发明人： Damian Pablo Yurzola , Rajeev Nagabhirava , Arjun Kapoor , Itai Dror , Annie Chi-San Chang , Peter Hwang , Jian Chen
IPC分类号： G06F11/00
CPC分类号： H03M7/30 , G06F11/1048 , G06F12/0246 , G06F2212/401 , G06F2212/403 , H03M13/35 , H03M13/6312
摘要： A method includes initiating a compression operation to compress data to be stored in a group of storage elements at a memory device that includes an error correction coding (ECC) engine. The method includes selecting one of a first mode of the ECC engine to generate a first number of parity bits and a second mode of the ECC engine to generate a second number of parity bits based on an extent of compression of the data. The method also includes encoding the compressed data to generate parity bits corresponding to the compressed data and storing the compressed data and the parity bits to the group of storage elements according to a page format that includes a data portion and a parity portion. The compressed data is stored in the data portion and at least some of the parity bits are stored in the parity portion.
摘要翻译：一种方法包括启动压缩操作以压缩要存储在包括纠错编码（ECC）引擎的存储器设备的一组存储元件中的数据。该方法包括选择ECC引擎的第一模式中的一个以产生第一数量的奇偶校验位，以及ECC引擎的第二模式，以基于数据的压缩程度生成第二数量的奇偶校验位。该方法还包括对压缩数据进行编码以产生与压缩数据相对应的奇偶校验位，并根据包括数据部分和奇偶校验部分的页格式将压缩数据和奇偶校验位存储到存储元件组。压缩数据被存储在数据部分中，并且至少一些奇偶校验位被存储在奇偶校验部分中。

8. 发明申请

US20060253522A1 Large number mutpilication method and device 有权
标题翻译：大数量多种方法和装置
公开(公告)号：US20060253522A1
公开(公告)日：2006-11-09
申请号：US11429190
申请日：2006-05-08
申请人： Itai Dror , Boris Dolgunov
发明人： Itai Dror , Boris Dolgunov
IPC分类号： G06F7/52
CPC分类号： G06F7/525
摘要： A signed multiplication method and a corresponding device for multiplying a first multiplicand with a second multiplicand. The device stores the first multiplicand in a first register as a first vector of at least one respective digit and storing the second multiplicand in a second register as a second vector of at least one respective digit, each digit having a pre-determined number of bits. The method further converts the digits of the first vector and the second vector to corresponding digits of one bit less each than the pre-determined number of bits. A processor effects signed multiplication of the multiplicands.
摘要翻译：一种有符号乘法方法和用于将第一被乘数与第二被乘数相乘的相应装置。设备将第一被乘数存储在第一寄存器中作为至少一个相应数字的第一向量，并将第二被乘数存储在第二寄存器中作为至少一个相应数字的第二向量，每个数字具有预定数量的位。该方法还将第一向量和第二向量的数字转换成比预定位数少一位的相应位数。处理器对被乘数进行带符号乘法。

9. 发明授权

US07111166B2 Extending the range of computational fields of integers 有权
标题翻译：扩展整数的计算领域范围
公开(公告)号：US07111166B2
公开(公告)日：2006-09-19
申请号：US09854853
申请日：2001-05-14
申请人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexey Molchanov
发明人： Itai Dror , Carmi David Gressel , Michael Mostovoy , Alexey Molchanov
IPC分类号： G06F7/72 , H04K1/00
CPC分类号： G06F7/724 , G06F7/728
摘要： An extension of the serial/parallel Montgomery modular multiplication method with simultaneous reduction as previously implemented by the applicants, adapted innovatively to perform both in the prime number and in the GF(2q) polynomial based number field, in such a way as to simplify the flow of operands, by performing a multiple anticipatory function to enhance the previous modular multiplication procedures.
摘要翻译：串行/并行蒙哥马利模拟乘法的扩展，如先前由申请人实现的同时还原，适用于创新地在素数和基于GF（2Q）的多项式的数字字段中执行，以简化操作数的流动的方式，通过执行多预期功能来增强先前的乘法程序。

10. 发明授权

US5664017A Internationally regulated system for one to one cryptographic communications with national sovereignty without key escrow 失效
标题翻译：国际监管制度，一键加密通信与国家主权没有密钥托管
公开(公告)号：US5664017A
公开(公告)日：1997-09-02
申请号：US437223
申请日：1995-05-08
申请人： Carmi David Gressel , Itai Dror
发明人： Carmi David Gressel , Itai Dror
IPC分类号： H04L9/08 , H04L9/30 , H04L9/00
CPC分类号： H04L9/0833 , H04L9/088
摘要： An encryption method and apparatus for generating an encrypted message which is controllably decryptable, comprising providing at least one agency public key to at least one decrypting agency entity respectively and to each of a first plurality of subscriber entities and to each of a second plurality of regulator entities, providing an ID, a public key and a private key for each of the first plurality of subscribers and each of the second plurality of regulators, for each subscriber entity and for each regulator entity, employing at least one agency public key to encrypt the entity's private key and for each individual subscriber entity and for each individual regulator entity, generating a certificate attesting, for all other entities, to the individual entity's status, ID, public key and encrypted private key.
摘要翻译：一种用于生成可控制地解密的加密消息的加密方法和装置，包括分别向至少一个解密机构实体提供至少一个代理公共密钥，并分别向第一多个订户实体和第二多个调节器实体，为每个订户实体和每个调节器实体提供用于第一多个订户和第二多个调节器中的每一个的ID，公钥和私钥，使用至少一个代理公钥来加密实体的私钥和每个单独的订户实体和每个单独的调节器实体，为所有其他实体生成证明对于各个实体的状态，ID，公开密钥和加密私钥的证书。

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