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1. 发明申请

US20070097875A1 Efficient probabilistic duplicate packet detector in computer networks 失效
标题翻译：计算机网络中的高效概率重复数据包检测器
公开(公告)号：US20070097875A1
公开(公告)日：2007-05-03
申请号：US11264529
申请日：2005-11-01
申请人： Carl Bender , Fu Chang , Kevin Gildea , Rama Govindaraju , Jay Herring , Peter Hochschild , Richard Swetz
发明人： Carl Bender , Fu Chang , Kevin Gildea , Rama Govindaraju , Jay Herring , Peter Hochschild , Richard Swetz
IPC分类号： H04L12/26
CPC分类号： H04L29/06 , H04L1/0057 , H04L1/0061 , H04L1/0079 , H04L69/326 , H04L2001/0092
摘要： In order to solve the problem of the detection of the arrival of duplicate data packets in an interconnected, multinode data processing system, each data packet is provided with a field of r bits that are randomly generated for each data packet. However, one of the packets is provided with a field that is computed from the other randomly generated field entries in a checksum computation which yields a selected nonzero checksum value. A running checksum at the receiver is used to determine whether or not, after the receipt of the specified number, k, of data packets, a duplicate packet has been received.
摘要翻译：为了解决在互连的多节点数据处理系统中检测到重复数据分组的问题的问题，每个数据分组被提供有为每个数据分组随机生成的r比特的字段。然而，其中一个分组被提供有一个字段，该字段是在产生选定的非零校验和值的校验和计算中的其他随机生成的字段条目中计算的。在接收机上运行的校验和用于确定在接收到数据包的指定数量k之后是否已经接收到重复分组。

2. 发明申请

US20050254492A1 Methods for routing packets on a linear array of processors 失效
标题翻译：在线性阵列处理器上路由数据包的方法
公开(公告)号：US20050254492A1
公开(公告)日：2005-11-17
申请号：US11186693
申请日：2005-07-21
申请人： Monty Denneau , Peter Hochschild , Richard Swetz , Henry Warren
发明人： Monty Denneau , Peter Hochschild , Richard Swetz , Henry Warren
IPC分类号： G06F15/173 , H04L12/56
CPC分类号： G06F15/17381 , G06F15/17337
摘要： There is provided a method for routing packets on a linear array of N processors connected in a nearest neighbor configuration. The method includes the step of, for each end processor of the array, connecting unused outputs to corresponding unused inputs. For each axis required to directly route a packet from a source to a destination processor, the following steps are performed. It is determined whether a result of directly sending a packet from an initial processor to a target processor is less than or greater than N/2 moves, respectively. The initial processor is the source processor in the first axis, and the target processor is the destination processor in the last axis. The packet is directly sent from the initial processor to the target processor, when the result is less than N/2 moves. The packet is indirectly sent so as to wrap around each end processor, when the result is greater than N/2 moves. The method may optionally include the step of randomly sending the packet using either of the sending steps, when the result is equal to N/2 moves and N is an even number.
摘要翻译：提供了一种用于在以最近邻配置连接的N个处理器的线性阵列上路由分组的方法。该方法包括对于阵列的每个终端处理器将未使用的输出连接到相应的未使用的输入的步骤。对于将数据包从源直接路由到目标处理器所需的每个轴，执行以下步骤。确定是否将分组从初始处理器直接发送到目标处理器的结果分别小于或大于N / 2移动。初始处理器是第一个轴中的源处理器，目标处理器是最后一个轴上的目标处理器。当结果小于N / 2移动时，数据包从初始处理器直接发送到目标处理器。当结果大于N / 2移动时，数据包被间接发送以便包围每个终端处理器。该方法可以可选地包括当结果等于N / 2移动并且N是偶数时，使用任一发送步骤随机发送分组的步骤。

3. 发明申请

US20100027735A1 RAM BASED IMPLEMENTATION FOR SCALABLE, RELIABLE HIGH SPEED EVENT COUNTERS 失效
标题翻译：基于RAM的可扩展，可靠的高速事件计数器的实现
公开(公告)号：US20100027735A1
公开(公告)日：2010-02-04
申请号：US12183748
申请日：2008-07-31
申请人： Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
发明人： Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
IPC分类号： H03K21/00
CPC分类号： H03K21/00 , G06F11/348 , G06F2201/86 , G06F2201/88 , H03K23/42
摘要： There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.
摘要翻译：这里广泛考虑了一种布置，其中每个事件源馈送小的专用“预计数器”，而实际计数保持在64位宽的RAM中。这种实施方式优选地可以包括以预定的固定顺序简单地扫过预先计数器的状态机。优选地，状态机将访问每个预计数器，将来自预计数器的值添加到相应的RAM位置，然后清除预计数器。因此，预计数器仅需要足够宽，使得即使在最大事件速率下，在“扫描器”状态机访问预先计数器之前，预计数器将不能包裹（即，达到容量或溢出）计数器。

4. 发明授权

US08660234B2 RAM based implementation for scalable, reliable high speed event counters 失效
标题翻译：基于RAM的实现可扩展，可靠的高速事件计数器
公开(公告)号：US08660234B2
公开(公告)日：2014-02-25
申请号：US12183748
申请日：2008-07-31
申请人： Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
发明人： Carl Alfred Bender , Peter Heiner Hochschild , Ashutosh Misra , Richard Swetz
IPC分类号： H03K21/00
CPC分类号： H03K21/00 , G06F11/348 , G06F2201/86 , G06F2201/88 , H03K23/42
摘要： There is broadly contemplated herein an arrangement whereby each event source feeds a small dedicated “pre-counter” while an actual count is kept in a 64-bit wide RAM. Such an implementation preferably may involve a state machine that simply sweeps through the pre-counters, in a predetermined fixed order. Preferably, the state machine will access each pre-counter, add the value from the pre-counter to a corresponding RAM location, and then clear the pre-counter. Accordingly, the pre-counters merely have to be wide enough such that even at a maximal event rate, the pre-counter will not be able to wrap (i.e., reach capacity or overflow) before the “sweeper” state machine accesses the pre-counter.
摘要翻译：这里广泛考虑了一种布置，其中每个事件源馈送小的专用“预计数器”，而实际计数保持在64位宽的RAM中。这种实施方式优选地可以包括以预定的固定顺序简单地扫过预先计数器的状态机。优选地，状态机将访问每个预计数器，将来自预计数器的值添加到相应的RAM位置，然后清除预计数器。因此，预计数器仅需要足够宽，使得即使在最大事件速率下，在“扫描器”状态机访问预先计数器之前，预计数器将不能包裹（即，达到容量或溢出）计数器。

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