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1. 发明申请

US20080195848A1 Vertical and Horizontal Pipelining in a System for Performing Modular Multiplication 失效
标题翻译：用于执行模块化乘法的系统中的垂直和水平流水线
公开(公告)号：US20080195848A1
公开(公告)日：2008-08-14
申请号：US11673752
申请日：2007-02-12
申请人： Camil Fayad , John K. Li , Siegfried Sutter , Tamas Visegrady
发明人： Camil Fayad , John K. Li , Siegfried Sutter , Tamas Visegrady
IPC分类号： G06F9/302
CPC分类号： G06F9/3001 , G06F7/722
摘要： The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the chaining together of processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a pardonable chain with separate parts for processing factors of the modulus.
摘要翻译：将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为每个处理元件的两个子阶段同时操作并且处理元件链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链接的处理元件被构造成提供具有用于处理模量因子的单独部件的可赦免链。

2. 发明授权

US07783864B2 Vertical and horizontal pipelining in a system for performing modular multiplication 失效
标题翻译：用于执行模数乘法的系统中的垂直和水平流水线
公开(公告)号：US07783864B2
公开(公告)日：2010-08-24
申请号：US11673752
申请日：2007-02-12
申请人： Camil Fayad , John K. Li , Siegfried Sutter , Tamas Visegrady
发明人： Camil Fayad , John K. Li , Siegfried Sutter , Tamas Visegrady
IPC分类号： G06F9/44 , G06F7/38
CPC分类号： G06F9/3001 , G06F7/722
摘要： The partitioning of large arrays in the hardware structure, for multiplication and addition, into smaller structures results in a multiplier design which includes a series of nearly identical processing elements linked together in a chained fashion. As a result of simultaneous operation in two subphases per processing element and the chaining together of processing elements, the overall structure is operable in a pipelined fashion to improve throughput and speed. The chained processing elements are constructed so as to provide a pardonable chain with separate parts for processing factors of the modulus.
摘要翻译：将硬件结构中的大阵列用于乘法和加法分割成更小的结构导致乘法器设计，其包括以链式方式链接在一起的一系列几乎相同的处理元件。作为每个处理元件的两个子阶段同时操作并且处理元件链接在一起的结果，整体结构以流水线方式操作以提高生产量和速度。链接的处理元件被构造成提供具有用于处理模量因子的单独部件的可赦免链。

3. 发明授权

US07890559B2 Forward shifting of processor element processing for load balancing 失效
标题翻译：用于负载平衡的处理器元件处理的前向移位
公开(公告)号：US07890559B2
公开(公告)日：2011-02-15
申请号：US11615587
申请日：2006-12-22
申请人： Camil Fayad , John K. Li , Siegfried K. H. Sutter , Tamas Visegrady
发明人： Camil Fayad , John K. Li , Siegfried K. H. Sutter , Tamas Visegrady
IPC分类号： G06F17/00
CPC分类号： G06F9/5083
摘要： A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.
摘要翻译：特别适用于执行模乘法的数据处理系统，特别是用于加密目的的数字处理系统包括多个独立的串行连接的处理元件，其经由控制机构以循环方式提供数据，该控制机制能够从一组寄存器到串行连接的处理元件的串联中的较早的寄存器，在预定次数的周期结束。

4. 发明申请

US20080152127A1 FORWARD SHIFTING OF PROCESSOR ELEMENT PROCESSING FOR LOAD BALANCING 失效
标题翻译：处理器元件处理负载平衡的前向移位
公开(公告)号：US20080152127A1
公开(公告)日：2008-06-26
申请号：US11615587
申请日：2006-12-22
申请人： Camil Fayad , John K. Li , Siegfried K.H. Sutter , Tamas Visegrady
发明人： Camil Fayad , John K. Li , Siegfried K.H. Sutter , Tamas Visegrady
IPC分类号： H04L9/28 , G06F7/72 , G06F5/01
CPC分类号： G06F9/5083
摘要： A data processing system, which is particularly useful for carrying out modular multiplication, especially for cryptographic purposes, comprises a plurality of independent, serially connected processing elements which are provided with data in a cyclical fashion via a control mechanism that is capable of transferring data from a set of registers to earlier ones in the series of the serially connected processing elements, at the end of a predetermined number of cycles.
摘要翻译：特别适用于执行模乘法的数据处理系统，特别是用于加密目的的数字处理系统包括多个独立的串行连接的处理元件，其经由控制机构以循环方式提供数据，该控制机制能够从一组寄存器到串行连接的处理元件的串联中的较早的寄存器，在预定次数的周期结束。

5. 发明授权

US07873830B2 Methods for coordinating access to memory from at least two cryptography secure processing units 失效
标题翻译：用于协调从至少两个加密安全处理单元访问存储器的方法
公开(公告)号：US07873830B2
公开(公告)日：2011-01-18
申请号：US11331918
申请日：2006-01-13
申请人： Camil Fayad , John K. Li , Siegfried Sutter
发明人： Camil Fayad , John K. Li , Siegfried Sutter
IPC分类号： H04L9/32 , G06F9/50 , G06F15/167 , G06F13/00
CPC分类号： G06F21/76 , G06F21/72 , G06F21/79
摘要： Electronic circuit chips which include cryptography functions are arranged in multichip configurations through the utilization of a shared external memory. Security of the chips is preserved via a handshaking protocol which permits each chip to access limited portions of the memory as defined in a way that preserves the same high security level as the tamper proof chips themselves. The chips may be operated to work on different tasks or to work on the same task thus providing a mechanism for trading off speed versus redundancy where desired.
摘要翻译：包括加密功能的电子电路芯片通过利用共享的外部存储器而被布置成多芯片配置。通过握手协议来保护芯片的安全性，该握手协议允许每个芯片访问存储器的有限部分，其以与防篡改芯片本身保持相同的高安全级别的方式定义。芯片可以被操作以在不同的任务上工作或者在相同的任务上工作，从而提供了一种用于在需要时对速度与冗余进行交换的机制。

6. 发明授权

US07818574B2 System and method for providing dynamically authorized access to functionality present on an integrated circuit chip 有权
标题翻译：用于提供对集成电路芯片上存在的功能的动态授权访问的系统和方法
公开(公告)号：US07818574B2
公开(公告)日：2010-10-19
申请号：US10938808
申请日：2004-09-10
申请人： Camil Fayad , John K. Li , Siegfried Sutter
发明人： Camil Fayad , John K. Li , Siegfried Sutter
IPC分类号： H04L9/32
CPC分类号： G06F21/72 , G06F2221/2115 , H04L9/3263 , H04L2209/56
摘要： A mechanism is provided in which access to the functionality present on an integrated circuit chip is controllable via an encrypted certificate of authority which includes time information indicating allowable periods of operation or allowable duration of operation. The chip includes at least one cryptographic engine and at least one processor. The chip also contains hard coded cryptographic keys including a chip private key, a chip public key and a third party's public key. The chip is also provided with a battery backed up volatile memory which contains information which is used to verify authority for operation. The certificate of authority is also used to control not only the temporal aspects of operation but is also usable to control access to certain functionality that may be present on the chip, such as access to some or all of the cryptographic features provided in conjunction with the presence of the cryptographic engine, such as key size.
摘要翻译：提供了一种机制，其中通过加密的授权证书来控制存在于集成电路芯片上的功能，其包括指示允许的操作周期或允许的操作持续时间的时间信息。该芯片包括至少一个加密引擎和至少一个处理器。该芯片还包含硬编码密码密钥，包括芯片私钥，芯片公钥和第三方的公钥。该芯片还配有电池备份的易失性存储器，其中包含用于验证操作权限的信息。授权证书也不仅用于控制操作的时间方面，而且还可用于控制对可能存在于芯片上的某些功能的访问，诸如访问与结合在一起提供的一些或全部密码特征加密引擎的存在，如密钥大小。

7. 发明授权

US07870395B2 Load balancing for a system of cryptographic processors 失效
标题翻译：加密处理器系统的负载平衡
公开(公告)号：US07870395B2
公开(公告)日：2011-01-11
申请号：US11551432
申请日：2006-10-20
申请人： Thomas J. Dewkett , Camil Fayad , John K. Li , Siegfried K. H. Sutter , Phil C. Yeh
发明人： Thomas J. Dewkett , Camil Fayad , John K. Li , Siegfried K. H. Sutter , Phil C. Yeh
IPC分类号： G06F12/14 , G06F15/167 , G06F15/80 , G06F15/82
CPC分类号： G06F21/72 , G06F9/5083
摘要： In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.
摘要翻译：在一组加密处理器的阵列中，每个组中的处理器一起工作，但通过外部共享存储器安全地连接。每个组中的处理器包括能够以流水线方式运行的加密引擎。请求块形式的指令以平衡方式提供给阵列，以确保处理器是占用处理指令。

8. 发明授权

US08532288B2 Selectively isolating processor elements into subsets of processor elements 失效
标题翻译：将处理器元件选择性地隔离成处理器元件的子集
公开(公告)号：US08532288B2
公开(公告)日：2013-09-10
申请号：US11565918
申请日：2006-12-01
申请人： Camil Fayad , John K. Li , Siegfried K. H. Sutter , Phil C. Yeh
发明人： Camil Fayad , John K. Li , Siegfried K. H. Sutter , Phil C. Yeh
IPC分类号： G06F21/00
CPC分类号： G06F7/722 , G06F2207/382
摘要： A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks that are smaller than the maximum capability of the engine in terms of bits multiplied at one time. The serially connected hardware is thus partitioned on the fly to process a variety of cryptographic key sizes while still maintaining all of the hardware in an active processing state.
摘要翻译：控制模N加法的加密引擎，其被构造为多个几乎相同的串行连接的处理元件，以便以一次乘以比特乘以引擎的最大能力的块来接受输入。因此，串行连接的硬件在飞行中进行分区以处理各种加密密钥大小，同时仍然保持所有硬件处于主动处理状态。

9. 发明申请

US20080130874A1 RUNTIME CONFIGURABILITY FOR CRT & NON CRT MODE 失效
标题翻译： CRT和非CRT模式的运行配置
公开(公告)号：US20080130874A1
公开(公告)日：2008-06-05
申请号：US11565918
申请日：2006-12-01
申请人： Camil Fayad , John K. Li , Siegfried K.H. Sutter , Phil C. Yeh
发明人： Camil Fayad , John K. Li , Siegfried K.H. Sutter , Phil C. Yeh
IPC分类号： H04L9/06
CPC分类号： G06F7/722 , G06F2207/382
摘要： A cryptographic engine for modulo N multiplication, which is structured as a plurality of almost identical, serially connected Processing Elements, is controlled so as to accept input in blocks that are smaller than the maximum capability of the engine in terms of bits multiplied at one time. The serially connected hardware is thus partitioned on the fly to process a variety of cryptographic key sizes while still maintaining all of the hardware in an active processing state.
摘要翻译：控制模N加法的加密引擎，其被构造为多个几乎相同的串行连接的处理元件，以便以一次乘以比特乘以引擎的最大能力的块来接受输入。因此，串行连接的硬件在飞行中进行分区以处理各种加密密钥大小，同时仍然保持所有硬件处于主动处理状态。

10. 发明申请

US20080098233A1 LOAD BALANCING FOR A SYSTEM OF CRYPTOGRAPHIC PROCESSORS 失效
标题翻译：用于制图处理器系统的负载平衡
公开(公告)号：US20080098233A1
公开(公告)日：2008-04-24
申请号：US11551432
申请日：2006-10-20
申请人： Thomas J. Dewkett , Camil Fayad , John K. Li , Siegfried K.H. Sutter , Phil C. Yeh
发明人： Thomas J. Dewkett , Camil Fayad , John K. Li , Siegfried K.H. Sutter , Phil C. Yeh
IPC分类号： G06F12/14 , H04L9/32 , G06F11/30
CPC分类号： G06F21/72 , G06F9/5083
摘要： In an array of groups of cryptographic processors, the processors in each group operate together but are securely connected through an external shared memory. The processors in each group include cryptographic engines capable of operating in a pipelined fashion. Instructions in the form of request blocks are supplied to the array in a balanced fashion to assure that the processors are occupied processing instructions.
摘要翻译：在一组加密处理器的阵列中，每个组中的处理器一起工作，但通过外部共享存储器安全地连接。每个组中的处理器包括能够以流水线方式运行的加密引擎。请求块形式的指令以平衡方式提供给阵列，以确保处理器是占用处理指令。

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