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1. 发明公开

EP0789878A4 HIERARCHICAL CROSSBAR SWITCH 失效
标题翻译：分层交叉道岔
公开(公告)号：EP0789878A4
公开(公告)日：2003-06-11
申请号：EP95939704
申请日：1995-10-31
申请人： CUBE INC I
发明人： WONG CHUN CHIU DANIEL , HSIEH WEN-JAI , HORNG CHI-SONG
IPC分类号： G06F13/36 , G06F15/173 , H03K19/173 , H03K19/177 , H05K1/00 , G06F13/00 , H04Q3/52
CPC分类号： G06F15/17375 , H03K19/1736 , H03K19/17704 , H05K1/0286
摘要： A hierarchical crossbar switch (30) includes several switch cells. Each array (A2(i,j)) including several pairs of signal ports (P0-P31) and provides a bidirectional signal path between the signal ports it interconnects when switched on by an enabling signal. A first memory array (62) stores input data indicating particular switch cells to be switched on. A second memory array (72) stores input data indicating particular ones of the switch arrays to be enabled. The crossbar switch (30) also includes a logic cell array that reads the data stored in the first and second memory and sends separate control signals to each switch cell. Each control signal switches on the switch cell to which it is sent when data in the first and second memory arrays which indicate both that the switch cell is to be switched on and that the switch cell array including the switch cell is to be enabled.

2. 发明公开

EP0789950A4 APPARATUS FOR PROGRAMMABLE CIRCUIT AND SIGNAL SWITCHING 失效
标题翻译：器件可编程电路和信号处理
公开(公告)号：EP0789950A4
公开(公告)日：2000-03-15
申请号：EP95939027
申请日：1995-10-31
申请人： CUBE INC I
发明人： HSIEH WEN-JAI , HORNG CHI-SONG , WONG CHUN CHIU DANIEL
IPC分类号： H03K19/177 , H03K19/173 , H03K19/0175
CPC分类号： H03K19/1736
摘要： A field programmable interconnect device (FPID 10) includes a set of ports (14) and an array of switch cells (16) for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray (fig. 6). Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a 'rapid connect' mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

3. 发明专利

DE69229873T2 未知
公开(公告)号：DE69229873T2
公开(公告)日：2000-05-04
申请号：DE69229873
申请日：1992-10-29
申请人： CUBE INC I
发明人： HSIEH WEN-JAI , JENQ YIH-CHYUN , HORNG CHI-SONG , LOFSTROM KEITH
IPC分类号： H03K19/173 , G06F13/40 , H03K19/0175 , H03K19/177 , G06F13/00
摘要： A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

4. 发明专利

DE69525062D1 未知
公开(公告)号：DE69525062D1
公开(公告)日：2002-02-21
申请号：DE69525062
申请日：1995-10-31
申请人： CUBE INC I
发明人： HSIEH WEN-JAI , HORNG CHI-SONG , WONG CHIU
IPC分类号： H03K19/177 , H03K19/173 , H03K19/0175
摘要： A field programmable interconnect device (FPID) includes a set of ports and an array of switch cells for selectively interconnecting pairs of the ports. The switch cells are organized into a hierarchy of subarrays, and a control cell is provided for each subarray. Each switch cell includes a crosspoint switch and a single-bit memory. A bit stored in the memory indicates whether the switch, when enabled, is to interconnect its pair of FPID I/O ports. A data bit stored in each control cell indicates whether all switching cells of an associated subarray are enabled. In a "rapid connect" mode of operation, the FPID sets the state of the bit stored in any individual switch or control cell in response to parallel input data identifying the cell and indicating the state of the bit to be stored in the cell. In the rapid connect mode, the FPID can be programmed to rapidly switch connections between individual lines or between parallel buses connected to its ports.

5. 发明专利

DE69229873D1 未知
公开(公告)号：DE69229873D1
公开(公告)日：1999-09-30
申请号：DE69229873
申请日：1992-10-29
申请人： CUBE INC I
发明人： HSIEH WEN-JAI , JENQ YIH-CHYUN , HORNG CHI-SONG , LOFSTROM KEITH
IPC分类号： H03K19/173 , G06F13/40 , H03K19/0175 , H03K19/177 , G06F13/00
摘要： A bi-directional buffer includes first and second unidirectional buffers connected for retransmitting signals in opposite directions between first and second buses. When an external bus driver pulls the first bus low, the first unidirectional buffer pulls the second bus low and generates a signal inhibiting the second unidirectional buffer from actively driving the first bus. When the external bus driver allows the first bus to return to the high logic level, the first unidirectional buffer temporarily supplies a high charging current to the second bus to quickly pull it up. Similarly, when an external bus driver pulls the second bus low, the second unidirectional buffer pulls the first bus low and generates a signal inhibiting the first unidirectional buffer from actively driving the second bus. When the external bus driver allows the second bus to return to the high logic level, the second buffer temporarily supplies a high charging current to the first bus to quickly pull it up. The bi-directional buffer includes a register for storing and reading out data representing successive logic states of a signal on the first bus, thereby providing a history of data appearing on the bus.

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