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    • 2. 发明申请
    • MOS TRANSISTOR
    • MOS晶体管
    • WO2012034371A1
    • 2012-03-22
    • PCT/CN2011/070949
    • 2011-02-12
    • CSMC TECHNOLOGIES FAB1 CO., LTD.CSMC TECHNOLOGIES FAB2 CO., LTD.WANG, GenyiWO, Tzong Shiann
    • WANG, GenyiWO, Tzong Shiann
    • H01L29/78H01L21/336
    • H01L29/7813H01L29/1095H01L29/41766H01L29/456H01L29/66727H01L29/66734
    • A metal oxide semiconductor (MOS) transistor (200) includes, in part, a semiconductor substrate (201), an epitaxial layer (202) formed above the substrate (201), a well region (203) formed in the epitaxial layer (202), a multitude of trenches (210) formed in the well region (203) with each trench (210) having formed therein a gate oxide layer (212) and a polysilicon gate (211), a multitude of contact holes (220) formed in the well region (203) wherein each contact hole (220) is positioned between a pair of adjacent trenches (210) and has disposed therein an adhesion layer (232) and a first metal layer (233) forming a metal plug, a multitude of body contact regions (204) positioned below the contact holes (220), and a multitude of source regions (231) formed in the well region (203). Each source region (231) is positioned between a trench (210) and a contact hole (220). The substrate (201), the epitaxial layer (202), and the source regions (231) are of a first conductivity type. The well region (203) and the body contact regions (204) are of a second conductivity type opposite the first conductivity type. The MOS transistor can minimize various parasitic effects and improve performance thereof. A method is also provided.
    • 金属氧化物半导体(MOS)晶体管(200)部分地包括半导体衬底(201),形成在衬底(201)上方的外延层(202),形成在外延层(202)中的阱区 ),形成在阱区(203)中的多个沟槽(210),其中每个沟槽(210)中形成有栅极氧化物层(212)和多晶硅栅极(211),形成多个接触孔(220) 在井区域(203)中,其中每个接触孔(220)位于一对相邻的沟槽(210)之间,并且在其中设置有粘合层(232)和形成金属插塞的第一金属层(233) 位于所述接触孔(220)下方的身体接触区域(204)以及形成在所述阱区域(203)中的多个源极区域(231)。 每个源极区域(231)位于沟槽(210)和接触孔(220)之间。 衬底(201),外延层(202)和源极区(231)是第一导电类型。 阱区(203)和体接触区(204)具有与第一导电类型相反的第二导电类型。 MOS晶体管可以最小化各种寄生效应并提高其性能。 还提供了一种方法。