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1. 发明申请

WO2010017020A1 MULTIPLE DATA CHANNEL MEMORY MODULE ARCHITECTURE 审中-公开
标题翻译：多个数据通道存储器模块架构
公开(公告)号：WO2010017020A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051096
申请日：2009-07-20
申请人： CONVEY COMPUTER , BREWER, Tony , ANDREWARTHA, J., Michael , O'LEARY, William, D. , DUGAN, Michael, K.
发明人： BREWER, Tony , ANDREWARTHA, J., Michael , O'LEARY, William, D. , DUGAN, Michael, K.
IPC分类号： G06F12/00
CPC分类号： G06F12/0811 , G06F12/04 , G06F12/0607 , G06F2212/283 , G11C7/1072
摘要： The present invention is directed generally to systems and methods which provide a memory module having multiple data channels that are independently accessible (i.e., a multi-data channel memory module). According to one embodiment, the multi-data channel memory module enables a plurality of independent sub-cache-block accesses to be serviced simultaneously. In addition, the memory architecture also supports cache-block accesses. For instance, multiple ones of the data channels may be employed for servicing a cache-block access. In one embodiment a DIMM architecture that comprises multiple data channels is provided. Each data channel supports a sub-cache-block access, and multiple ones of the data channels may be used for supporting a cache-block access. The plurality of data channels to a given DIMM may be used simultaneously to support different, independent memory access operations.
摘要翻译：本发明一般涉及提供具有独立可访问的多个数据信道（即，多数据信道存储器模块）的存储器模块的系统和方法。根据一个实施例，多数据通道存储器模块使多个独立的子高速缓存块访问同时被服务。此外，内存架构还支持高速缓存块访问。例如，可以使用多个数据信道来服务高速缓存块访问。在一个实施例中，提供了包括多个数据通道的DIMM架构。每个数据信道支持子缓存块访问，并且可以使用多个数据信道来支持高速缓存块访问。给定DIMM的多个数据信道可以同时使用以支持不同的独立存储器访问操作。

2. 发明申请

WO2010051166A1 CO-PROCESSOR INFRASTRUCTURE SUPPORTING DYNAMICALLY-MODIFIABLE PERSONALITIES 审中-公开
标题翻译：协同处理基础设施支持动态修改的个人
公开(公告)号：WO2010051166A1
公开(公告)日：2010-05-06
申请号：PCT/US2009/060811
申请日：2009-10-15
申请人： CONVEY COMPUTER , BREWER, Tony , WALLACH, Steven
发明人： BREWER, Tony , WALLACH, Steven
IPC分类号： G06F15/76
CPC分类号： G06F9/30036 , G06F9/30109 , G06F9/3877 , G06F9/3887 , G06F9/3897
摘要： A co-processor is provided that comprises one or more application engines that can be dynamically configured to a desired personality. For instance, the application engines may be dynamically configured to any of a plurality of different vector processing instruction sets, such as a single-precision vector processing instruction set and a double-precision vector processing instruction set. The co-processor further comprises a common infrastructure that is common across all of the different personalities, such as an instruction decode infrastructure, memory management infrastructure, system interface infrastructure, and/or scalar processing unit (that has a base set of instructions). Thus, the personality of the co-processor can be dynamically modified (by reconfiguring one or more application engines of the co-processor), while the common infrastructure of the co-processor remains consistent across the various personalities.
摘要翻译：提供了一种协处理器，其包括可被动态配置为期望个性的一个或多个应用引擎。例如，应用引擎可以被动态配置为多个不同的向量处理指令集中的任何一个，例如单精度向量处理指令集和双精度向量处理指令集。协处理器还包括在所有不同个性之间共同的公共基础设施，例如指令解码基础设施，存储器管理基础设施，系统接口基础设施和/或标量处理单元（具有基本指令集）。因此，协处理器的个性可以被动态修改（通过重新配置协处理器的一个或多个应用引擎），而协处理器的公共基础设施在各个人物之间保持一致。

3. 发明申请

WO2010017019A1 MEMORY INTERLEAVE FOR HETEROGENEOUS COMPUTING 审中-公开
标题翻译：用于异构计算的记忆交互
公开(公告)号：WO2010017019A1
公开(公告)日：2010-02-11
申请号：PCT/US2009/051095
申请日：2009-07-20
申请人： CONVEY COMPUTER , BREWER, Tony , MAGEE, Terrell , ANDREWARTHA, J., Michael
发明人： BREWER, Tony , MAGEE, Terrell , ANDREWARTHA, J., Michael
IPC分类号： G06F13/00
CPC分类号： G06F12/0607 , G06F12/0851
摘要： A memory interleave system for providing memory interleave for a heterogeneous computing system is provided. The memory interleave system effectively interleaves memory that is accessed by heterogeneous compute elements in different ways, such as via cache-block accesses by certain compute elements and via non-cache- block accesses by certain other compute elements. The heterogeneous computing system may comprise one or more cache-block oriented compute elements and one or more non- cache-block oriented compute elements that share access to a common main memory. The cache-block oriented compute elements access the memory via cache-block accesses (e.g., 64 bytes, per access), while the non-cache-block oriented compute elements access memory via sub-cache-block accesses (e.g., 8 bytes, per access). A memory interleave system is provided to optimize the interleaving across the system's memory banks to minimize hot spots resulting from the cache-block oriented and non-cache-block oriented accesses of the heterogeneous computing system.
摘要翻译：提供了一种用于为异构计算系统提供存储器交错的存储器交错系统。存储器交错系统有效地交织由异构计算元件以不同方式访问的存储器，例如经由某些计算元件的高速缓冲存储器块访问以及由某些其他计算元件的非高速缓存块访问。异构计算系统可以包括一个或多个面向高速缓存块的计算元件和一个或多个非高速缓存块定向的计算元件，其共享对公共主存储器的访问。面向缓存块的计算元件通过高速缓存块访问（例如，每个访问64字节）访问存储器，而非缓存块面向计算元件通过子高速缓存块访问访问存储器（例如，8字节，每次访问）。提供存储器交错系统以优化跨系统的存储体的交织，以最小化由异构计算系统的面向缓存块和非高速缓存块的存取导致的热点。

4. 发明申请

WO2013184380A2 SYSTEMS AND METHODS FOR EFFICIENT SCHEDULING OF CONCURRENT APPLICATIONS IN MULTITHREADED PROCESSORS 审中-公开
标题翻译：用于多步骤处理器中相关应用的有效调度的系统和方法
公开(公告)号：WO2013184380A2
公开(公告)日：2013-12-12
申请号：PCT/US2013/042439
申请日：2013-05-23
申请人： CONVEY COMPUTER
发明人： LEIDEL, John, D. , WADLEIGH, Kevin, R. , BOLDING, Joe , BREWER, Tony , WALKER, Dean, E.
IPC分类号： G06F9/30
CPC分类号： G06F9/30145 , G06F8/45 , G06F9/3009 , G06F9/30167 , G06F9/30185 , G06F9/3851
摘要： Systems and methods which provide a modular processor framework and instruction set architecture designed to efficiently execute applications whose memory access patterns are irregular or non-unit stride as disclosed. A hybrid multithreading framework (HMTF) of embodiments provides a framework for constructing tightly coupled, chip-multithreading (CMT) processors that contain specific features well-suited to hiding latency to main memory and executing highly concurrent applications. The HMTF of embodiments includes an instruction set designed specifically to exploit the high degree of parallelism and concurrency control mechanisms present in the HMTF hardware modules. The instruction format implemented by a HMTF of embodiments is designed to give the architecture, the runtime libraries, and/or the application ultimate control over how and when concurrency between thread cache units is initiated. For example, one or more bit of the instruction payload may be designated as a context switch bit (CTX) for expressly controlling context switching.
摘要翻译：提供模块化处理器框架和指令集架构的系统和方法，被设计为有效地执行如所公开的存储器访问模式是不规则的或非单位的步骤的应用。实施例的混合多线程框架（HMTF）提供了构建紧密耦合的芯片多线程（CMT）处理器的框架，其包含非常适合于隐藏主存储器的延迟并执行高并发应用的特定特征。实施例的HMTF包括专门设计用于利用HMTF硬件模块中存在的高度并行性和并发控制机制的指令集。由实施例的HMTF实现的指令格式被设计为给出架构，运行时库和/或应用程序对线程高速缓存单元何时启动和何时并发的最终控制。例如，指令有效载荷的一个或多个位可以被指定为用于明确地控制上下文切换的上下文切换位（CTX）。

5. 发明申请

WO2009029698A1 COMPILER FOR GENERATING AN EXECUTABLE COMPRISING INSTRUCTIONS FOR A PLURALITY OF DIFFERENT INSTRUCTION SETS 审中-公开
标题翻译：用于生成多个不同指令集的可执行包含指令的编译器
公开(公告)号：WO2009029698A1
公开(公告)日：2009-03-05
申请号：PCT/US2008/074566
申请日：2008-08-28
申请人： CONVEY COMPUTER , BREWER, Tony , WALLACH, Steven
发明人： BREWER, Tony , WALLACH, Steven
IPC分类号： G06F9/44
CPC分类号： G06F8/447
摘要： A software compiler is provided that is operable for generating an executable that comprises instructions for a plurality of different instruction sets as may be employed by different processors in a multi-processor system. The compiler may generate an executable that includes a first portion of instructions to be processed by a first instruction set (such as a first instruction set of a first processor in a multi-processor system) and a second portion of instructions to be processed by a second instruction set (such as a second instruction set of a second processor in a multi-processor system). Such executable may be generated for execution on a multi-processor system that comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set, and at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured.
摘要翻译：提供了一种软件编译器，其可操作用于生成包括多处理器系统中不同处理器可能采用的多个不同指令集的指令的可执行程序。编译器可以生成包括由第一指令集（诸如多处理器系统中的第一处理器的第一指令集）处理的指令的第一部分的指令和由第一指令处理的指令的第二部分第二指令集（诸如多处理器系统中的第二处理器的第二指令集）。这样的可执行程序可以被生成用于在包括至少一个主机处理器的多处理器系统上执行，所述至少一个主机处理器可以包括诸如公知的x86指令集之类的固定指令集，以及至少一个协处理器，其包括动态地可配置逻辑，使协处理器的指令集能够动态重新配置。

6. 发明申请

WO2010051167A1 DYNAMICALLY-SELECTABLE VECTOR REGISTER PARTITIONING 审中-公开
标题翻译：动态可选选择矢量寄存器分区
公开(公告)号：WO2010051167A1
公开(公告)日：2010-05-06
申请号：PCT/US2009/060820
申请日：2009-10-15
申请人： CONVEY COMPUTER , BREWER, Tony , WALLACH, Steven
发明人： BREWER, Tony , WALLACH, Steven
IPC分类号： G06F15/76
CPC分类号： G06F9/30036 , G06F9/30112 , G06F9/3012 , G06F9/30189 , G06F9/3877 , G06F9/3885 , G06F9/3887 , G06F9/3897 , G06F15/8084
摘要： The present invention is directed generally to dynamically-selectable vector register partitioning, and more specifically to a processor infrastructure (e.g., co-processor infrastructure in a multi-processor system) that supports dynamic setting of vector register partitioning to any of a plurality of different vector partitioning modes. Thus, rather than being restricted to a fixed vector register partitioning mode, embodiments of the present invention enable a processor to be dynamically set to any of a plurality of different vector partitioning modes. Thus, for instance, different vector register partitioning modes may be employed for different applications being executed by the processor, and/or different vector register partitioning modes may even be employed for use in processing different vector oriented operations within a given applications being executed by the processor, in accordance with certain embodiments of the present invention.
摘要翻译：本发明一般地涉及动态可选择的向量寄存器划分，更具体地涉及支持向量寄存器划分到多个不同的任何一个的动态设置的处理器基础设施（例如，多处理器系统中的协处理器基础设施）矢量分割模式。因此，本发明的实施例不是限于固定矢量寄存器分割模式，而是能够将处理器动态地设置为多个不同的矢量分割模式中的任何一个。因此，例如，可以对由处理器执行的不同应用采用不同的向量寄存器分割模式，和/或可以采用不同的矢量寄存器分割模式来用于处理在由处理器，根据本发明的某些实施例。

7. 发明申请

WO2009088682A1 MICROPROCESSOR ARCHITECTURE HAVING ALTERNATIVE MEMORY ACCESS PATHS 审中-公开
标题翻译：具有替代存储器访问码的微处理器架构
公开(公告)号：WO2009088682A1
公开(公告)日：2009-07-16
申请号：PCT/US2008/087233
申请日：2008-12-17
申请人： CONVEY COMPUTER , WALLACH, Steven , BREWER, Tony
发明人： WALLACH, Steven , BREWER, Tony
IPC分类号： G06F13/00
CPC分类号： G06F12/0888 , G06F12/0844 , G06F12/0877 , G06F12/1027 , G06F2212/60 , G06F2212/68
摘要： The present invention is directed to a system and method which employ two memory access paths: a cache-access path in which block data is fetched from main memory for loading to a cache, and a direct-access path in which Individually addressed data is fetched from main memory. The system may comprise one or more processor cores that utilize the cache-access path for accessing data. The system may further comprise at least one heterogeneous functional unit that is operable to utilize the direct-access path for accessing data. In certain embodiments, the one or more processor cores, cache, and the at least one heterogeneous functional unit may be Included on a common semiconductor die (e.g., part of an integrated circuit). Embodiments of the present invention enable improved system performance by selectively employing the cache-access path for certain instructions while selectively employing the direct-access path for other instruction.
摘要翻译：本发明涉及采用两个存储器访问路径的系统和方法：缓存访问路径，其中从主存储器取出块数据以加载到高速缓存，以及直接访问路径，其中获取单独寻址的数据从主记忆。系统可以包括利用高速缓存访问路径访问数据的一个或多个处理器核。系统还可以包括至少一个异构功能单元，其可操作以利用直接访问路径来访问数据。在某些实施例中，一个或多个处理器核，高速缓存和至少一个异构功能单元可以被包括在公共半导体管芯（例如，集成电路的一部分）上。本发明的实施例通过在选择性地使用用于其他指令的直接访问路径的情况下选择性地采用某些指令的高速缓存访问路径来实现改进的系统性能。

8. 发明申请

WO2009036043A1 DISPATCH MECHANISM FOR DISPATCHING INSTRUCTIONS FROM A HOST PROCESSOR TO A CO-PROCESSOR 审中-公开
标题翻译：用于将主机处理器指示给协处理器的分配机制
公开(公告)号：WO2009036043A1
公开(公告)日：2009-03-19
申请号：PCT/US2008/075828
申请日：2008-09-10
申请人： CONVEY COMPUTER , WALLACH, Steven , BREWER, Tony
发明人： WALLACH, Steven , BREWER, Tony
IPC分类号： G06F12/00
CPC分类号： G06F9/3877 , G06F9/30185 , G06F9/3802 , G06F9/3879 , G06F9/3897 , G06F12/0855 , G06F12/10 , G06F15/7867
摘要： A mechanism is provided for dispatching instructions of an executable from a host processor to a heterogeneous co-processor. In certain embodiments, cache coherency is maintained between the host processor and the heterogeneous co-processor, and such cache coherency is leveraged for dispatching instructions of an executable for processing by the co-processor. In certain embodiments a designated portion of memory (e.g., UCB) is utilized, wherein a host processor may place information in such UCB and the co¬ processor can retrieve information from the UCB (and vice-versa). The UCB may thus be used to dispatch instructions of an executabl for processing by the co-processor. In certain embodiments, the co-processor comprises dynamically reconfigurable logic, enabling the co-processor's instruction set to be dynamically changed, and the dispatching operation may identify one of a plurality of predefined instruction sets to load onto the co-processor
摘要翻译：提供了一种用于将可执行程序的指令从主处理器分派到异构协处理器的机制。在某些实施例中，在主处理器和异构协处理器之间保持高速缓存一致性，并且利用这种高速缓存一致性来调度可执行程序的指令以供协处理器处理。在某些实施例中，利用指定的存储器部分（例如，UCB），其中主处理器可以将信息放置在这样的UCB中，并且协处理器可以从UCB检索信息（反之亦然）。因此，UCB可以用于调度执行器的指令以供协处理器处理。在某些实施例中，协处理器包括动态可重配置逻辑，使协处理器的指令集能够动态地改变，并且调度操作可以识别多个预定义指令集中的一个以加载到协处理器

9. 发明申请

WO2009026196A1 MULTI-PROCESSOR SYSTEM HAVING AT LEAST ONE PROCESSOR THAT COMPRISES A DYNAMICALLY RECONFIGURABLE INSTRUCTION SET 审中-公开
标题翻译：具有至少一个包含动态可重构指令集的处理器的多处理器系统
公开(公告)号：WO2009026196A1
公开(公告)日：2009-02-26
申请号：PCT/US2008/073423
申请日：2008-08-18
申请人： CONVEY COMPUTER , WALLACH, Steven , BREWER, Tony
发明人： WALLACH, Steven , BREWER, Tony
IPC分类号： G06F15/00
CPC分类号： G06F15/7867 , G06F9/24 , G06F9/3881 , G06F9/3897
摘要： A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co¬ processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.
摘要翻译：多处理器系统包括至少一个主机处理器，其可以包括固定指令集，诸如公知的x86指令集。该系统还包括至少一个协处理器，其包括使协处理器的指令集能够动态重新配置的动态可重配置逻辑。以这种方式，至少一个主机处理器和至少一个动态可重配置协处理器是具有不同指令集的异构处理器。此外，在异构主机和协处理器之间保持高速缓存一致性。并且，单个可执行文件可以包含由多处理器系统处理的指令，其中指令的一部分由主机处理器处理，并且指令的一部分由协处理器处理。

10. 发明公开

EP2191380A1 MULTI-PROCESSOR SYSTEM HAVING AT LEAST ONE PROCESSOR THAT COMPRISES A DYNAMICALLY RECONFIGURABLE INSTRUCTION SET 有权转让
标题翻译：与动态NEUKONFIGURIERBAREM命令设置至少一个处理器，多个处理器系统
公开(公告)号：EP2191380A1
公开(公告)日：2010-06-02
申请号：EP08827665.4
申请日：2008-08-18
申请人： Convey Computer
发明人： WALLACH, Steven , BREWER, Tony
IPC分类号： G06F15/00
CPC分类号： G06F15/7867 , G06F9/24 , G06F9/3881 , G06F9/3897
摘要： A multi-processor system comprises at least one host processor, which may comprise a fixed instruction set, such as the well-known x86 instruction set. The system further comprises at least one co-processor, which comprises dynamically reconfigurable logic that enables the co-processor's instruction set to be dynamically reconfigured. In this manner, the at least one host processor and the at least one dynamically reconfigurable co-processor are heterogeneous processors having different instruction sets. Further, cache coherency is maintained between the heterogeneous host and co¬ processors. And, a single executable file may contain instructions that are processed by the multi-processor system, wherein a portion of the instructions are processed by the host processor and a portion of the instructions are processed by the co-processor.

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