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1. 发明申请

WO2018194970A1 CALIBRATION FOR AMPLIFIER WITH CONFIGURABLE FINAL OUTPUT STAGE 审中-公开
公开(公告)号：WO2018194970A1
公开(公告)日：2018-10-25
申请号：PCT/US2018/027763
申请日：2018-04-16
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZHU, Lei
发明人： ZHU, Lei , ZHAO, Xin , DAS, Tejasvi , MORTON, Alan Mark , FEI, Xiaofan
IPC分类号： H03F1/02 , H03F3/21 , H03F3/72 , H03F3/217
摘要： A method for offset calibration may include decoupling a modulator input of a first path from a first stage output, coupling a second path output to the modulator input, applying a common-mode voltage to a second path input, receiving a calibration signal from the modulator output generated in response to the common-mode voltage, and modifying one or more parameters of the modulator to compensate for an offset between the first path and the second path indicated by the calibration signal. A method for gain calibration may include decoupling a modulator input from a first stage output, decoupling a second path from the first stage output, applying a first test signal to the modulator input, applying a second test signal to a second path input, wherein the second test signal is of opposite phase as the first test signal, coupling a second path output to an amplifier input via a calibration feedback network, receiving a calibration signal from the first stage output generated in response to the first test signal and the second test signal, and modifying one or more parameters of the second path to compensate for a difference in respective gains of the modulator and the second path indicated by the calibration signal.

2. 发明申请

WO2018191119A3 SWITCHING IN AMPLIFIER WITH CONFIGURABLE FINAL OUTPUT STAGE 审中-公开
公开(公告)号：WO2018191119A3
公开(公告)日：2018-10-18
申请号：PCT/US2018/026486
申请日：2018-04-06
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZHU, Lei
发明人： ZHU, Lei , ZHAO, Xin , MORTON, Alan Mark , DAS, Tejasvi , HE, Ku , FEI, Xiaofan
IPC分类号： H03F1/02 , H03F3/217 , H03F3/30
摘要： An amplifier may include a final output stage switchable among a plurality of modes comprising a mode which is enabled by coupling an output driver to an output of the final output stage and a preconditioning circuit coupled to the output of the final output stage. The preconditioning circuit may be configured to precondition at least one of a voltage and a current of the output of the final output stage prior to coupling the output driver to the output of the final output stage to limit audio artifacts caused by switching the final output stage to the mode or may be configured to perform a switching sequence to switch between a first mode and a second mode of the plurality of modes, such that at all points of the switching sequence, output terminals of the output of the final output stage have a known impedance.

3. 发明申请

WO2018191119A2 SWITCHING IN AMPLIFIER WITH CONFIGURABLE FINAL OUTPUT STAGE 审中-公开
公开(公告)号：WO2018191119A2
公开(公告)日：2018-10-18
申请号：PCT/US2018/026486
申请日：2018-04-06
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZHU, Lei
发明人： ZHU, Lei , ZHAO, Xin , MORTON, Alan Mark , DAS, Tejasvi , HE, Ku , FEI, Xiaofan
IPC分类号： H03F1/02 , H03F3/217 , H03F3/30
摘要： An amplifier may include a final output stage switchable among a plurality of modes comprising a mode which is enabled by coupling an output driver to an output of the final output stage and a preconditioning circuit coupled to the output of the final output stage. The preconditioning circuit may be configured to precondition at least one of a voltage and a current of the output of the final output stage prior to coupling the output driver to the output of the final output stage to limit audio artifacts caused by switching the final output stage to the mode or may be configured to perform a switching sequence to switch between a first mode and a second mode of the plurality of modes, such that at all points of the switching sequence, output terminals of the output of the final output stage have a known impedance.

4. 发明申请

WO2018136237A1 CLOSED-LOOP DIGITAL COMPENSATION SCHEME 审中-公开
公开(公告)号：WO2018136237A1
公开(公告)日：2018-07-26
申请号：PCT/US2018/012375
申请日：2018-01-04
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZHU, Lei , ZHAO, Xin , MELANSON, John
发明人： ZHU, Lei , ZHAO, Xin , MELANSON, John
IPC分类号： H03F1/32 , H03F3/217 , H03F1/30 , H03F3/187
摘要： Resistor mismatch may be digitally compensated based on a known resistor mismatch, power supply information, and/or other operating parameters of the amplifier. The digital compensation may be applied to the digital input signal before conversion for processing and amplification in the analog domain. An amplifier with digital compensation for resistor mismatch may be used in a class-D amplifier with a closed loop and feedforward feedback. A class-D or other amplifier with digital compensation may be integrated with electronic devices such as mobile phones.

5. 发明申请

WO2020023615A1 GAIN CONTROL IN A CLASS-D OPEN-LOOP AMPLIFIER 审中-公开
公开(公告)号：WO2020023615A1
公开(公告)日：2020-01-30
申请号：PCT/US2019/043204
申请日：2019-07-24
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , ZHU, Lei
发明人： ZHU, Lei , DAS, Tejasvi , MELANSON, John, L. , SHUM, Wai-Shun, Wilson , BAI, Jing , ZHAO, Xin , FEI, Xiaofan
IPC分类号： H03F3/181 , H03F3/217 , H03G3/30
摘要： A system may include a digital modulator configured to modulate an input signal received at an input of the digital modulator to generate a modulated input signal at an output of the digital modulator, a digital gain element having a digital gain and coupled to the digital modulator, an open-loop Class-D amplifier coupled to an output of the digital modulator and configured to amplify the modulated input signal, wherein the open-loop Class-D amplifier is powered from a variable power supply having a variable supply voltage which is variable in response to one or more characteristics of the input signal, and a control circuit configured to control the digital gain to approximately cancel changes in an analog gain of the open-loop Class-D amplifier due to variation in the variable supply voltage in response to the one or more characteristics of the input signal.

6. 发明申请

WO2018136682A1 OFFSET CALIBRATION FOR AMPLIFIER AND PRECEDING CIRCUIT 审中-公开
公开(公告)号：WO2018136682A1
公开(公告)日：2018-07-26
申请号：PCT/US2018/014326
申请日：2018-01-19
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZHU, Lei
发明人： ZHU, Lei , HE, Ku , ZHAO, Xin , SONG, Miao , SINGH, Saurabh , JAYAKUMAR, Vinod
IPC分类号： H03F1/32 , H03F3/217 , H03F1/30 , H03F3/187
摘要： A method may include, in an apparatus comprising a closed loop amplifier and a signal processing block configured to generate an amplifier input signal as a function of an upstream signal received at an input of the signal processing block, in a calibration mode of the apparatus: decoupling a second stage input of the amplifier from a first stage output of the amplifier; determining an offset signal that when applied to the input of a signal processing block as the upstream signal generates approximately zero as an intermediate signal generated by the first stage of the amplifier; and controlling one or more parameters of the apparatus based on the offset signal to compensate for an offset of at least one of the first stage and the signal processing block.

7. 发明申请

WO2018063878A1 AMPLIFIER WITH CONFIGURABLE FINAL OUTPUT STAGE 审中-公开
标题翻译：具有可配置的最终输出级的放大器
公开(公告)号：WO2018063878A1
公开(公告)日：2018-04-05
申请号：PCT/US2017/052439
申请日：2017-09-20
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR, LTD. , ZHAO, Xin
发明人： ZHAO, Xin , DAS, Tejasvi , FEI, Xiaofan , MORTON, Alan Mark
IPC分类号： H03F3/72 , H03F3/217 , H03F1/32 , H03F3/181
摘要： An amplifier may include a first stage configured to receive an input signal at an amplifier input and generate an intermediate signal which is a function of the input signal, and a final output stage configured to generate an output signal which is a function of the intermediate signal at an amplifier output, and a signal feedback network coupled between the amplifier output and input. The final output stage may be switchable among a plurality of modes including at least a first mode in which the final output stage generates the output signal as a modulated output signal which is a function of the intermediate signal, and a second mode in which the final output stage generates the output signal as an unmodulated output signal which is a function of the intermediate signal. Structure of the feedback network and the first stage may remain static when switching between modes.
摘要翻译：放大器可以包括：第一级，被配置为在放大器输入处接收输入信号并且生成作为输入信号的函数的中间信号;以及最终输出级，被配置为生成输出信号这是放大器输出端的中间信号的函数，以及连接在放大器输出端和输入端之间的信号反馈网络。最终输出级可以在包括至少第一模式和第二模式的多种模式之间切换，所述第一模式中最终输出级生成作为作为中间信号的函数的调制输出信号的输出信号，以及第二模式，输出级产生作为中间信号的函数的未调制输出信号的输出信号。当模式切换时，反馈网络和第一阶段的结构可能保持不变。

8. 发明申请

WO2019203887A1 A DUAL-PATH PULSE WIDTH MODULATION SYSTEM 审中-公开
公开(公告)号：WO2019203887A1
公开(公告)日：2019-10-24
申请号：PCT/US2018/054413
申请日：2018-10-04
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , DAS, Tejasvi
发明人： DAS, Tejasvi , MORTON, Alan Mark , ZHAO, Xin , ZHU, Lei , FEI, Xiaofan , GABORIAU, Johann G. , MELANSON, John L. , VELLANKI, Amar
IPC分类号： H03F3/183 , H03F3/217
摘要： A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, wherein a first gain of the first path and a second gain of the second path are approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

9. 发明申请

WO2019079035A1 CALIBRATION OF A DUAL-PATH PULSE WIDTH MODULATION SYSTEM 审中-公开
公开(公告)号：WO2019079035A1
公开(公告)日：2019-04-25
申请号：PCT/US2018/054186
申请日：2018-10-03
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , DAS, Tejasvi
发明人： DAS, Tejasvi , MORTON, Alan Mark , ZHAO, Xin , ZHU, Lei , FEI, Xiaofan , GABORIAU, Johann G. , MELANSON, John L. , VELLANKI, Amar
IPC分类号： H03F3/183 , H03F3/217
摘要： A system may include a digital pulse width modulator subsystem, a first path coupled to an output of the digital pulse width modulator subsystem and configured to drive an open-loop driver stage, a second path coupled to the output of the digital pulse width modulator subsystem and configured to drive a closed-loop analog pulse width modulator, a controller to select between the first path and the second path for processing a signal based on one or more characteristics of the signal, and a calibration subsystem configured to calibrate at least one of a first gain of the first path and a second gain of the second path in order that the first gain and the second gain are at least approximately equal at the time of switching selection between the first path and the second path or vice versa, in order to minimize artifacts due to the switching.

10. 发明申请

WO2019160684A1 DUAL BOOTSTRAPPING FOR AN OPEN-LOOP PULSE WIDTH MODULATION DRIVER 审中-公开
公开(公告)号：WO2019160684A1
公开(公告)日：2019-08-22
申请号：PCT/US2019/015795
申请日：2019-01-30
申请人： CIRRUS LOGIC INTERNATIONAL SEMICONDUCTOR LTD. , BAI, Jing
发明人： BAI, Jing , DAS, Tejasvi , ZHAO, Xin , ZHU, Lei , FEI, Xiaofan
IPC分类号： H03F3/183 , H03F3/217
摘要： A driver system may include a first n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a first terminal of a supply voltage and configured to drive the output when the first n-type field-effect transistor is activated, a second n-type field-effect transistor coupled at its non-gate terminals between an output of the driver system and a second terminal of the supply voltage and configured to drive the output when the second n-type field-effect transistor is activated, a high-side capacitor coupled to the output of the driver system, and a low-side capacitor coupled to the second terminal of the supply voltage, wherein the high-side capacitor and the low-side capacitor are configured to track and correct for mismatches between a first resistance of the first n-type field-effect transistor and a second resistance of the second n-type field-effect transistor.

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