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1. 发明申请

US20110007064A1 GATE LINE DRIVING MODULE FOR LIQUID CRYSTAL DISPLAY AND LIQUID CRYSTAL DISPLAY USING THE SAME 有权
标题翻译：用于液晶显示器的门式驱动模块和使用该液晶显示器的液晶显示器
公开(公告)号：US20110007064A1
公开(公告)日：2011-01-13
申请号：US12826594
申请日：2010-06-29
申请人： CHIEN-HSUEH CHIANG , SZ-HSIAO CHEN
发明人： CHIEN-HSUEH CHIANG , SZ-HSIAO CHEN
IPC分类号： G06F3/038
CPC分类号： G09G3/3674 , G02F1/13454 , G02F2202/103 , G09G3/3266 , G09G3/3677 , G09G2300/0408 , G09G2310/0278 , G09G2310/0286 , G09G2320/043 , G09G2330/02 , G09G2330/06
摘要： A gate line driving module used on a liquid crystal display uses clock signal sources in replacement of a high level gate power source, such that the phenomenon of device characteristic drift occurring in the foregoing related art is avoided. The gate line driving module includes a plurality of odd-pixel gate line driving circuits, a plurality of even-pixel gate line driving circuits, and an auxiliary gate line driving circuit. A pair of neighboring odd-pixel gate line driving circuit and even-pixel gate line driving circuit exchange output signals thereof with each other in a forward or feedback manner for ensuring that each the odd-pixel gate line driving circuit and each the even-pixel gate line driving circuit are driven once. The auxiliary gate line driving circuit is used for ensuring that signal iteration of the gate line driving module is under normal operation.
摘要翻译：在液晶显示器上使用的栅极线驱动模块使用时钟信号源代替高电平门电源，从而避免了在上述现有技术中出现的器件特性偏移现象。栅极线驱动模块包括多个奇数像素栅极线驱动电路，多个偶数像素栅极线驱动电路和辅助栅极线驱动电路。一对相邻的奇数像素栅极线驱动电路和偶数像素栅极线驱动电路以正向或反向的方式彼此交换输出信号，以确保每个奇数像素栅极线驱动电路和每个偶数像素栅极线驱动电路被驱动一次。辅助栅极线驱动电路用于确保栅极线驱动模块的信号迭代正常工作。

2. 发明申请

US20110141075A1 SHIFT REGISTER AND DRIVING CIRCUIT FOR LIQUID CRYSTAL DISPLAY 有权
标题翻译：液晶显示器的移位寄存器和驱动电路
公开(公告)号：US20110141075A1
公开(公告)日：2011-06-16
申请号：US12965913
申请日：2010-12-12
申请人： CHIEN-HSUEH CHIANG
发明人： CHIEN-HSUEH CHIANG
IPC分类号： G09G5/00 , G11C19/00 , G11C19/28
CPC分类号： G11C19/28 , G09G3/3677 , G09G3/3688 , G09G2310/0286
摘要： A shift register includes first and second shift register units. Two adjacent first shift register units respectively receive a first and second clock signal. Two adjacent second shift register units respectively receive a third and a fourth clock signal. Each first and second shift register unit includes a cascade data input terminal, a cascade data output terminal, an output terminal used to output a shift signal, a feedback terminal, and a reset terminal. The shift signals of the Mth second and Nth first shift register unit are respectively fed back to the feedback terminal of the (N+1)th first and Mth second shift register unit. The reset terminal and the cascade data output terminal of the Nth first and Mth second shift register unit are respectively connected to the output terminal and the cascade data input terminal of (N+1)th first and (M+1)th second shift register unit.
摘要翻译：移位寄存器包括第一和第二移位寄存器单元。两个相邻的第一移位寄存器单元分别接收第一和第二时钟信号。两个相邻的第二移位寄存器单元分别接收第三和第四时钟信号。每个第一和第二移位寄存器单元包括级联数据输入端子，级联数据输出端子，用于输出移位信号的输出端子，反馈端子和复位端子。第M和第N移位寄存器单元的移位信号分别反馈到第（N + 1）个第一和第M个第二移位寄存器单元的反馈端。第N个第一和第M个第二移位寄存器单元的复位端子和级联数据输出端分别连接到第（N + 1）个第一和第（M + 1）个第二移位寄存器的输出端和级联数据输入端单元。

3. 发明申请

US20110090139A1 ACTIVE DEVICE ARRAY SUBSTRATE, LIQUID CRYSTAL DISPLAY PANEL AND ELECTRONIC APPARATUS 审中-公开
标题翻译：主动装置阵列底板，液晶显示面板和电子装置
公开(公告)号：US20110090139A1
公开(公告)日：2011-04-21
申请号：US12900501
申请日：2010-10-08
申请人： CHIEN-HSUEH CHIANG
发明人： CHIEN-HSUEH CHIANG
IPC分类号： G09G3/36 , G09G3/20
CPC分类号： G09G3/3648 , G09G2300/0426 , G09G2330/08
摘要： An active device array substrate includes a plurality of pixel units, a plurality of scan lines, a plurality of data lines. Each of the pixel units has an active device. The pixel units are arranged to form at least one group of a first pixel unit column and a second pixel unit column adjacent to each other, and the pixel units in the first pixel unit column and the second pixel unit column are vertically arranged. The scan lines and the data lines electrically connected to the corresponding active devices of the pixel units. Herein, the data line connected to the active devices of the pixel units of the first pixel unit column and the data line connected to the active devices of the pixel units of the second pixel unit column form a closed loop.
摘要翻译：有源器件阵列衬底包括多个像素单元，多条扫描线，多条数据线。每个像素单元具有有源器件。像素单元被布置成形成彼此相邻的第一像素单元列和第二像素单元列的至少一组，并且垂直地布置第一像素单元列和第二像素单元列中的像素单元。扫描线和数据线电连接到像素单元的相应的有源器件。这里，连接到第一像素单元列的像素单元的有源器件的数据线和连接到第二像素单元列的像素单元的有源器件的数据线形成闭环。

4. 发明申请

US20110129052A1 SHIFT REGISTER WITH TWO-WAY TRANSMISSION AND LIQUID CRYSTAL DISPLAY DEVICE USING SAME 有权
标题翻译：具有两路传输和液晶显示装置的移位寄存器
公开(公告)号：US20110129052A1
公开(公告)日：2011-06-02
申请号：US12955915
申请日：2010-11-30
申请人： CHIEN-HSUEH CHIANG
发明人： CHIEN-HSUEH CHIANG
IPC分类号： G11C19/00
CPC分类号： G11C19/28
摘要： A shift register includes individually connected shift register units. Each shift register unit includes a switching unit, a pre-charging unit, a pulse signal output unit, a low level voltage signal control unit, a first clock pulse signal input, a second clock pulse signal input, and an output. The first and the second clock pulse signal inputs respectively receive a first clock signal and a second clock signal, the first clock signal and the second clock signal having reverse clock pulses during each clock cycle. The switching unit receives at least one external starting signal and a high level signal, when the at least one external starting signal is high level, the switching unit is turned on and outputs the high level signal to the pre-charging unit. When the second clock signal is high level, the pre-charging unit receives the high level signal and charges, and when the first clock signal is high level, the pre-charging unit discharges. The pulse signal output unit receives the first clock signal and outputs the first clock signal to the output after the pre-charging unit charges and before the pre-charging unit finishes discharging. The low level voltage signal control unit receives the first clock signal and the second clock signal, after the pre-charging unit finishes discharging, the low level voltage signal control unit pulls down a voltage level on the output at low level when the second clock signal are high level.
摘要翻译：移位寄存器包括单独连接的移位寄存器单元。每个移位寄存器单元包括开关单元，预充电单元，脉冲信号输出单元，低电平电压信号控制单元，第一时钟脉冲信号输入，第二时钟脉冲信号输入和输出。第一和第二时钟脉冲信号输入分别在每个时钟周期期间接收第一时钟信号和第二时钟信号，第一时钟信号和第二时钟信号具有反向时钟脉冲。开关单元接收至少一个外部启动信号和高电平信号，当至少一个外部启动信号为高电平时，开关单元导通，并将高电平信号输出到预充电单元。当第二时钟信号为高电平时，预充电单元接收高电平信号并充电，并且当第一时钟信号为高电平时，预充电单元放电。脉冲信号输出单元接收第一时钟信号，并且在预充电单元充电之后并且在预充电单元完成放电之前将第一时钟信号输出到输出。低电平电压信号控制单元接收第一时钟信号和第二时钟信号，在预充电单元完成放电之后，低电平电压信号控制单元在第二时钟信号时将低电平上的电压电平拉低是高水平的

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