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1. 发明申请

WO2005060655A2 DETERMINISTIC JITTER EQUALIZER 审中-公开
标题翻译：决定性智力平衡机
公开(公告)号：WO2005060655A2
公开(公告)日：2005-07-07
申请号：PCT/US2004/042174
申请日：2004-12-14
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY , BUCKWALTER, James , HAJIMIRI, Seyed, Ali , ANALUI, Behnam
发明人： BUCKWALTER, James , HAJIMIRI, Seyed, Ali , ANALUI, Behnam
IPC分类号： H03H11/26 , H04B1/10 , H04L1/20 , H04L7/033
CPC分类号： H03H11/265 , H04L1/205 , H04L7/0337
摘要： An equalizer for serial data communications can be configured to compensate for the effects of deterministic jitter. The equalizer can be configured to compensate a received serial data stream for the effects of data-dependent jitter as well as duty cycle distortion jitter. The equalizer can be configured to determine the value of one or more previously received symbols and compare them to a recovered symbol. The equalizer can adjust a variable delay positioned in the serial data path to introduce a delay into the data path that is based in part on the received data stream. The equalizer can be configured to vary the delay when any of the one or more previously received symbols is different from the recovered symbol, and can be configured to maintain a constant delay if the one or more previously received symbols is the same as the recovered symbol.
摘要翻译：串行数据通信的均衡器可以配置为补偿确定性抖动的影响。均衡器可以配置为补偿接收的串行数据流，以获得与数据相关的抖动以及占空比失真抖动的影响。均衡器可以被配置为确定一个或多个先前接收的符号的值，并将其与恢复的符号进行比较。均衡器可以调整位于串行数据路径中的可变延迟，以将延迟引入到部分基于所接收的数据流的数据路径中。均衡器可以被配置为当一个或多个先前接收到的符号中的任一个与恢复的符号不同时，改变延迟，并且如果一个或多个先前接收到的符号与恢复的符号相同，则可以配置为保持恒定的延迟。

2. 发明申请

WO2003091871A3 SYSTEM AND METHOD FOR CLOCKLESS DATA RECOVERY 审中-公开
公开(公告)号：WO2003091871A3
公开(公告)日：2003-11-06
申请号：PCT/US2003/012932
申请日：2003-04-25
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY , HAJIMIRI, Seyed-Ali , ANALUI, Behnam
发明人： HAJIMIRI, Seyed-Ali , ANALUI, Behnam
IPC分类号： G06F7/00
摘要： A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.

3. 发明申请

WO2003091871A2 SYSTEM AND METHOD FOR CLOCKLESS DATA RECOVERY 审中-公开
标题翻译：用于无数据恢复的系统和方法
公开(公告)号：WO2003091871A2
公开(公告)日：2003-11-06
申请号：PCT/US2003/012932
申请日：2003-04-25
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY , HAJIMIRI,Seyed-Ali , ANALUI, Behnam
发明人： HAJIMIRI,Seyed-Ali , ANALUI, Behnam
IPC分类号： G06F7/00
CPC分类号： H04L7/02 , H04L7/0337
摘要： A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.
摘要翻译：提供了一种用于无时钟同步数据恢复的系统。该系统包括输入速率解复用器，其接收以比特率发送的数据位的串行数据流，并从串行数据流生成两个或更多个并行数据流。耦合到输入速率解复用器的一个或多个延迟器每个接收所产生的并行串行数据流中的一个并延迟数据位并将其馈送回输入速率解复用器。

4. 发明申请

WO2003015260A1 METHOD AND APPARATUS FOR A MULTI-POLE BANDWIDTH ENHANCEMENT TECHNIQUE FOR WIDEBAND AMPLIFICATION 审中-公开
标题翻译：用于宽带放大的多波段增强技术的方法和装置
公开(公告)号：WO2003015260A1
公开(公告)日：2003-02-20
申请号：PCT/US2002/024998
申请日：2002-08-06
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY , ANALUI, Behnam , HAJIMIRI, Seyed-Ali
发明人： ANALUI, Behnam , HAJIMIRI, Seyed-Ali
IPC分类号： H03F3/04
CPC分类号： H03F1/42 , H03F1/086 , H03F2200/36
摘要： The gain-bandwidth (GBW) limitation problem inherent in all amplifiers is overcome to provide wideband amplifiers with specified characteristics for the transfer function. Parasitic capacitances of transistors are absorbed or incorporated into the design of the passive networks (22), which are inserted between the gain staps of the amplifier. The component values are determined based on conventional low-pass filter structures. A prototype CMOS transimpedance amplifier implemented using the developed technique achieves over 9GHz bandwidth and 54dB transimpedance gain from a O.5pF photo-diode capacitance.
摘要翻译：克服所有放大器固有的增益带宽（GBW）限制问题，为传输功能提供具有指定特性的宽带放大器。晶体管的寄生电容被吸收或并入无源网络（22）的设计中，被动网络（22）被插入在放大器的增益槽之间。基于传统的低通滤波器结构确定分量值。使用开发的技术实现的原型CMOS跨阻放大器实现了超过9GHz的带宽和来自O.5pF光电二极管电容的54dB跨阻增益。

5. 发明公开

EP1502180A2 SYSTEM AND METHOD FOR CLOCKLESS DATA RECOVERY 有权
标题翻译： DEVICE AND METHOD FOR时钟丢失数据恢复
公开(公告)号：EP1502180A2
公开(公告)日：2005-02-02
申请号：EP03724242.7
申请日：2003-04-25
申请人： California Institute of Technology
发明人： HAJIMIRI,Seyed-Ali , ANALUI, Behnam
IPC分类号： G06F7/00 , H04L7/02
CPC分类号： H04L7/02 , H04L7/0337
摘要： A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.

6. 发明授权

EP1502180B1 SYSTEM AND METHOD FOR CLOCKLESS DATA RECOVERY 有权
标题翻译： DEVICE AND METHOD FOR时钟丢失数据恢复
公开(公告)号：EP1502180B1
公开(公告)日：2008-06-18
申请号：EP03724242.7
申请日：2003-04-25
申请人： CALIFORNIA INSTITUTE OF TECHNOLOGY
发明人： HAJIMIRI,Seyed-Ali , ANALUI, Behnam
IPC分类号： G06F7/00 , H04L7/02
CPC分类号： H04L7/02 , H04L7/0337
摘要： A system for clockless synchronous data recovery is provided. The system includes an input rate demultiplexer receiving a serial data stream of bits of data transmitted at a bit rate and generating two or more parallel data streams from the serial data stream. One or more delays coupled to the input rate demultiplexer each receives one of the generated parallel serial data streams and delays bits of data and feeds them back to the input rate demultiplexer.

7. 发明公开

EP1709758A2 DETERMINISTIC JITTER EQUALIZER 审中-公开
标题翻译：确定性抖动均衡器
公开(公告)号：EP1709758A2
公开(公告)日：2006-10-11
申请号：EP04818035.0
申请日：2004-12-14
申请人： The California Institute of Technology
发明人： BUCKWALTER, James , HAJIMIRI, Seyed, Ali , ANALUI, Behnam
IPC分类号： H04B17/00 , H04L25/00 , H03H7/30
CPC分类号： H03H11/265 , H04L1/205 , H04L7/0337
摘要： An equalizer for serial data communications can be configured to compensate for the effects of deterministic jitter. The equalizer can be configured to compensate a received serial data stream for the effects of data-dependent jitter as well as duty cycle distortion jitter. The equalizer can be configured to determine the value of one or more previously received symbols and compare them to a recovered symbol. The equalizer can adjust a variable delay positioned in the serial data path to introduce a delay into the data path that is based in part on the received data stream. The equalizer can be configured to vary the delay when any of the one or more previously received symbols is different from the recovered symbol, and can be configured to maintain a constant delay if the one or more previously received symbols is the same as the recovered symbol.

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