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1. 发明授权

US07916538B2 Memory device employing NVRAM and flash memory cells 失效
标题翻译：采用NVRAM和闪存单元的存储器件
公开(公告)号：US07916538B2
公开(公告)日：2011-03-29
申请号：US12337950
申请日：2008-12-18
申请人： Byung-gil Jeon , Byung-jun Min , Hong-sik Jeong
发明人： Byung-gil Jeon , Byung-jun Min , Hong-sik Jeong
IPC分类号： G11C16/04
CPC分类号： G11C16/0483 , G11C11/005 , G11C16/0416
摘要： A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括NAND闪存单元部分，该NAND闪存单元部分包括多个串联闪存单元的第一列和包含多个第二列NVRAM单元的非易失性随机存取存储器（NVRAM）单元部分。闪存单元和NVRAM单元被布置成使得各个字线连接到各行中的每个行中的闪存单元和NVRAM单元，其可对应于包括闪存单元和NVRAM单元的页单元。

2. 发明申请

US20090190401A1 Memory device employing NVRAM and flash memory cells 失效
标题翻译：采用NVRAM和闪存单元的存储器件
公开(公告)号：US20090190401A1
公开(公告)日：2009-07-30
申请号：US12337950
申请日：2008-12-18
申请人： Byung-gil Jeon , Byung-jun Min , Hong-sik Jeong
发明人： Byung-gil Jeon , Byung-jun Min , Hong-sik Jeong
IPC分类号： G11C16/04 , G11C7/00 , G11C8/10 , G11C16/06
CPC分类号： G11C16/0483 , G11C11/005 , G11C16/0416
摘要： A memory device includes a memory cell array including a NAND flash cell portion including a plurality of first columns of serially-connected flash memory cells and a non-volatile random access memory (NVRAM) cell portion including a plurality of second columns of NVRAM cells. The flash memory cells and the NVRAM cells are arranged such that respective word lines are connected to flash memory cells and NVRAM cells in each of respective rows, which may correspond to page units including flash memory cells and NVRAM cells.
摘要翻译：存储器件包括存储单元阵列，该存储单元阵列包括NAND闪存单元部分，该NAND闪存单元部分包括多个串联闪存单元的第一列和包括多个第二列NVRAM单元的非易失性随机存取存储器（NVRAM）单元部分。闪存单元和NVRAM单元被布置成使得各个字线连接到各行中的每个行中的闪存单元和NVRAM单元，其可对应于包括闪存单元和NVRAM单元的页单元。

3. 发明授权

US5835400A Ferroelectric memory devices having nondestructive read capability and methods of operating same 失效
标题翻译：具有非破坏性读取能力的铁电存储器件及其操作方法
公开(公告)号：US5835400A
公开(公告)日：1998-11-10
申请号：US947607
申请日：1997-10-09
申请人： Byung-gil Jeon , Chul-sung Park
发明人： Byung-gil Jeon , Chul-sung Park
IPC分类号： G11C14/00 , G11C7/00 , G11C11/22
CPC分类号： G11C11/22
摘要： Ferroelectric memory devices contain an array of ferroelectric memory cells therein and control circuits for enabling the performance of nondestructive read operations. The memory cells of a device contain a ferroelectric memory cell and each memory cell contains a ferroelectric capacitor having a first electrode electrically coupled to a plate line and an access transistor electrically coupled in series between a bit line and a second electrode of the ferroelectric capacitor. A decoder circuit is also provided. The decoder circuit is electrically coupled to the access transistor of the memory cell by a word line and performs the function of, among other things, turning on the access transistor during a read time interval. According to a preferred aspect of the present invention, a pulse generator circuit is provided for initiating nondestructive reading of a quiescent polarization state of the ferroelectric capacitor by applying a single read pulse to the plate line to sweep a polarization state of the ferroelectric capacitor along a noncoercive portion of its hysteresis curve, during the read time interval. A sense amplifier circuit is also provided. The sense amplifier circuit also has a first input electrically coupled to the bit line and a second input electrically coupled to a reference signal line. The sense amplifier performs the function of driving the bit line to a first potential which represents the quiescent polarization state of the ferroelectric capacitor, preferably before termination of the single read pulse.
摘要翻译：铁电存储器件包含其中的铁电存储器单元阵列和用于实现非破坏性读取操作的控制电路。器件的存储单元包含铁电存储单元，并且每个存储单元包含铁电电容器，该铁电电容器具有电耦合到板线的第一电极和电阻耦合在铁电电容器的位线和第二电极之间的存取晶体管。还提供一个解码器电路。解码器电路通过字线电耦合到存储单元的存取晶体管，并且执行在读取时间间隔期间接通存取晶体管的功能。根据本发明的优选方面，提供了一种脉冲发生器电路，用于通过向板线施加单个读取脉冲来对铁电电容器的静态极化状态进行非破坏性读取，以扫描强电介质电容器的极化状态沿着在读取时间间隔期间其滞后曲线的非矫正部分。还提供读出放大器电路。感测放大器电路还具有电耦合到位线的第一输入和电耦合到参考信号线的第二输入。读出放大器执行将位线驱动到表示铁电电容器的静态极化状态的第一电位的功能，优选在单个读取脉冲结束之前。

4. 发明授权

US09842659B2 Non-volatile memory device for detecting progressive error, memory system, and method of operating the non-volatile memory device 有权
公开(公告)号：US09842659B2
公开(公告)日：2017-12-12
申请号：US14616281
申请日：2015-02-06
申请人： Sang-wan Nam , Byung-gil Jeon , Dae-seok Byeon
发明人： Sang-wan Nam , Byung-gil Jeon , Dae-seok Byeon
IPC分类号： G11C11/34 , G11C29/02 , G11C29/12 , G11C29/50
CPC分类号： G11C29/025 , G11C2029/1202 , G11C2029/5006
摘要： Provided are a non-volatile memory device, a memory system, and a method of operating the non-volatile memory device. The method includes: performing a user operation according to at least one mode selected from among a writing mode, a reading mode, and an erasing mode with respect to a memory cell array; setting up voltages of a plurality of word lines; floating at least one word line from among the plurality of word lines, the voltages of which are set up, according to the at least one selected mode; and detecting whether the at least one word line has a progressive defect, according to a result of detecting a voltage level of the at least one floated word line.

5. 发明授权

US06215693B1 Methods of operating ferroelectric memory devices having reconfigurable bit lines 失效
标题翻译：具有可重构位线的铁电存储器件的操作方法
公开(公告)号：US06215693B1
公开(公告)日：2001-04-10
申请号：US09566669
申请日：2000-05-08
申请人： Yeon-bae Chung , Byung-gil Jeon
发明人： Yeon-bae Chung , Byung-gil Jeon
IPC分类号： G11C1122
CPC分类号： G11C11/22
摘要： Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations. The reference cell array also preferably comprises a plurality of ferroelectric reference cells which each comprise first and second access transistors therein and first and second ferroelectric capacitors therein which store complementary states. During a reading operation, the complementary data stored in the first and second ferroelectric reference capacitors is simultaneously provided to a portion of a first bit line which is electrically connected to a second input of a sense amplifier. Data in a memory cell within the array is also provided to another portion of the first bit line which is electrically connected to a first input of the sense amplifier. The sense amplifier is then activated to amplify a difference in potential between the different portions of the first bit line as complementary signals and then the signals are provided as output data.
摘要翻译：集成电路存储器件包含铁电随机存取存储单元阵列和电耦合到多个位线的铁电参考单元阵列，耦合到多个位线的读出放大器和板/位线选择开关，用于配置所选择的位线作为板线，通过选择性地将多个位线中的第一位与读出放大器耦合，并且响应于列选择信号，通过有选择地将多个位线中的第二位与板线相耦合。包括选择开关和相关的驱动电路消除了提供额外的专用板线的需要，因为在读取和写入操作期间每个位线可以至少临时配置为板线。参考单元阵列还优选地包括多个铁电参考单元，每个铁电参考单元各自包括第一和第二存取晶体管，其中存储互补状态的第一和第二铁电电容器。在读取操作期间，存储在第一和第二铁电参考电容器中的互补数据同时被提供给电连接到读出放大器的第二输入端的第一位线的一部分。阵列内的存储单元中的数据也被提供给电连接到读出放大器的第一输入端的第一位线的另一部分。然后激活读出放大器以放大第一位线的不同部分之间的电位差作为互补信号，然后将该信号提供为输出数据。

6. 发明授权

US6097624A Methods of operating ferroelectric memory devices having reconfigurable bit lines 有权
标题翻译：具有可重构位线的铁电存储器件的操作方法
公开(公告)号：US6097624A
公开(公告)日：2000-08-01
申请号：US429860
申请日：1999-10-29
申请人： Yeon-bae Chung , Byung-gil Jeon
发明人： Yeon-bae Chung , Byung-gil Jeon
IPC分类号： G11C11/22
CPC分类号： G11C11/22
摘要： Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations. The reference cell array also preferably comprises a plurality of ferroelectric reference cells which each comprise first and second access transistors therein and first and second ferroelectric capacitors therein which store complementary states. During a reading operation, the complementary data stored in the first and second ferroelectric reference capacitors is simultaneously provided to a portion of a first bit line which is electrically connected to a second input of a sense amplifier. Data in a memory cell within the array is also provided to another portion of the first bit line which is electrically connected to a first input of the sense amplifier. The sense amplifier is then activated to amplify a difference in potential between the different portions of the first bit line as complementary signals and then the signals are provided as output data.
摘要翻译：集成电路存储器件包含铁电随机存取存储单元阵列和电耦合到多个位线的铁电参考单元阵列，耦合到多个位线的读出放大器和板/位线选择开关，用于配置所选择的位线作为板线，通过选择性地将多个位线中的第一位与读出放大器耦合，并且响应于列选择信号，通过有选择地将多个位线中的第二位与板线相耦合。包括选择开关和相关的驱动电路消除了提供额外的专用板线的需要，因为在读取和写入操作期间每个位线可以至少临时配置为板线。参考单元阵列还优选地包括多个铁电参考单元，每个铁电参考单元各自包括第一和第二存取晶体管，其中存储互补状态的第一和第二铁电电容器。在读取操作期间，存储在第一和第二铁电参考电容器中的互补数据同时被提供给电连接到读出放大器的第二输入端的第一位线的一部分。阵列内的存储单元中的数据也被提供给电连接到读出放大器的第一输入端的第一位线的另一部分。然后激活读出放大器以放大第一位线的不同部分之间的电位差作为互补信号，然后将该信号提供为输出数据。

7. 发明授权

US5978250A Ferroelectric memory devices having reconfigurable bit lines and methods of operating same 失效
标题翻译：具有可重构位线的铁电存储器件及其操作方法
公开(公告)号：US5978250A
公开(公告)日：1999-11-02
申请号：US932729
申请日：1997-09-17
申请人： Yeon-bae Chung , Byung-gil Jeon
发明人： Yeon-bae Chung , Byung-gil Jeon
IPC分类号： G11C14/00 , G11C11/21 , G11C11/22 , H01L21/8242 , H01L21/8246 , H01L21/8247 , H01L27/10 , H01L27/105 , H01L27/108 , H01L29/788 , H01L29/792
CPC分类号： G11C11/22
摘要： Integrated circuit memory devices contain a ferroelectric random access memory cell array and a ferroelectric reference cell array electrically coupled to a plurality of bit lines, a sense amplifier and a plate/bit line selection switch, coupled to the plurality of bit lines, for configuring selected bit lines as plate lines by selectively coupling first ones of the plurality of bit lines to the sense amplifier and by selectively coupling second ones of the plurality of bit lines to a plate line, in response to a column select signal. The inclusion of a selection switch and related driving circuits eliminates the need to provide extra dedicated plate lines because each of the bit lines can be at least temporarily configured as a plate line during reading and writing operations. The reference cell array also preferably comprises a plurality of ferroelectric reference cells which each comprise first and second access transistors therein and first and second ferroelectric capacitors therein which store complementary states. During a reading operation, the complementary data stored in the first and second ferroelectric reference capacitors is simultaneously provided to a portion of a first bit line which is electrically connected to a second input of a sense amplifier. Data in a memory cell within the array is also provided to another portion of the first bit line which is electrically connected to a first input of the sense amplifier. The sense amplifier is then activated to amplify a difference in potential between the different portions of the first bit line as complementary signals and then the signals are provided as output data.
摘要翻译：集成电路存储器件包含铁电随机存取存储单元阵列和电耦合到多个位线的铁电参考单元阵列，耦合到多个位线的读出放大器和板/位线选择开关，用于配置所选择的位线作为板线，通过选择性地将多个位线中的第一位与读出放大器耦合，并且响应于列选择信号，通过选择性地将多个位线中的第二位与板线耦合。包括选择开关和相关的驱动电路消除了提供额外的专用板线的需要，因为在读取和写入操作期间每个位线可以至少临时配置为板线。参考单元阵列还优选地包括多个铁电参考单元，每个铁电参考单元各自包括第一和第二存取晶体管，其中存储互补状态的第一和第二铁电电容器。在读取操作期间，存储在第一和第二铁电参考电容器中的互补数据同时被提供给电连接到读出放大器的第二输入端的第一位线的一部分。阵列内的存储单元中的数据也被提供给电连接到读出放大器的第一输入端的第一位线的另一部分。然后激活读出放大器以放大第一位线的不同部分之间的电位差作为互补信号，然后将该信号提供为输出数据。

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