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1. 发明授权

US07180327B2 Memory module system with efficient control of on-die termination 有权
标题翻译：内存模块系统，具有对片上终端的高效控制
公开(公告)号：US07180327B2
公开(公告)日：2007-02-20
申请号：US10997406
申请日：2004-11-24
申请人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
发明人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
IPC分类号： H03K17/16 , G11C8/12
CPC分类号： H04L25/0278 , G11C5/04 , G11C7/1078 , G11C7/1084
摘要： For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.
摘要翻译：对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

2. 发明授权

US07350120B2 Buffered memory module and method for testing same 有权
标题翻译：缓冲存储器模块和测试方法
公开(公告)号：US07350120B2
公开(公告)日：2008-03-25
申请号：US10833322
申请日：2004-04-28
申请人： Jeong-Hyeon Cho , Byung-Se So , Jae-Jun Lee
发明人： Jeong-Hyeon Cho , Byung-Se So , Jae-Jun Lee
IPC分类号： G11C29/00 , G01R31/02
CPC分类号： G11C29/48 , G11C2029/5602 , G11C2029/5606
摘要： A buffered memory module includes a buffer circuit mounted and a plurality of memory devices mounted on the first surface of the board, the memory devices being electrically connected to the buffer circuit. The memory module also includes a plurality of test pads located on a second surface of the board and electrically connected to the buffer circuit.
摘要翻译：缓冲存储器模块包括安装的缓冲电路和安装在板的第一表面上的多个存储器件，存储器件电连接到缓冲电路。存储器模块还包括位于板的第二表面上并电连接到缓冲电路的多个测试焊盘。

3. 发明申请

US20050212551A1 Memory module system with efficient control of on-die termination 有权
标题翻译：内存模块系统，具有对片上终端的高效控制
公开(公告)号：US20050212551A1
公开(公告)日：2005-09-29
申请号：US10997406
申请日：2004-11-24
申请人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
发明人： Byung-Se So , Jeong-Hyeon Cho , Jae-Jun Lee
IPC分类号： G06F12/00 , G11C5/00 , G11C7/10 , G11C11/401 , H03K19/003 , H04L25/02
CPC分类号： H04L25/0278 , G11C5/04 , G11C7/1078 , G11C7/1084
摘要： For ODT (on-die termination) control within a memory module system, just one pin from the memory controller is used for sending command signals indicating an activated one of the memory devices. The activated memory device includes components that are turned on for generating the ODT control signal for controlling an ODT circuit of inactivated memory device(s). The components for generating an ODT control signal within the inactivated memory devices are turned off for minimized power consumption.
摘要翻译：对于存储器模块系统内的ODT（片上终端）控制，仅使用来自存储器控制器的一个引脚来发送指示已激活的存储器件的命令信号。激活的存储器件包括被开启以产生用于控制非激活存储器件的ODT电路的ODT控制信号的组件。用于在非激活的存储器件内产生ODT控制信号的组件被关闭以最小化功率消耗。

4. 发明申请

US20050089106A1 Data transmission system and method 失效
标题翻译：数据传输系统及方法
公开(公告)号：US20050089106A1
公开(公告)日：2005-04-28
申请号：US10913359
申请日：2004-08-09
申请人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
IPC分类号： H04B3/50 , H04L25/14 , H04B1/69
CPC分类号： H04L25/14
摘要： A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.
摘要翻译：一种数据传输系统和方法，其特征在于使用多个差分输出放大器来传输根据从参考数据输出选通信号导出的控制信号而变化的差分数据信号，以及多个差分放大器以接收差分数据信号并检测这些变化以产生对应于数据输出选通信号的数据输入选通信号。

5. 发明授权

US07505521B2 Data transmission system and method 失效
标题翻译：数据传输系统及方法
公开(公告)号：US07505521B2
公开(公告)日：2009-03-17
申请号：US10913359
申请日：2004-08-09
申请人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jae-Jun Lee , Jong-Hoon Kim , Byung-Se So
IPC分类号： H04B3/00
CPC分类号： H04L25/14
摘要： A data transmission system and method characterized by the use of multiple differential output amplifiers to transmits differential data signals that vary in accordance with control signals derived from a reference data output strobe signal, and multiple differential amplifiers to receive the differential data signals and detect such variations to generate a data input strobe signal corresponding to the data output strobe signal.
摘要翻译：一种数据传输系统和方法，其特征在于使用多个差分输出放大器来传输根据从参考数据输出选通信号导出的控制信号而变化的差分数据信号，以及多个差分放大器以接收差分数据信号并检测这些变化以产生对应于数据输出选通信号的数据输入选通信号。

6. 发明申请

US20060059298A1 Memory module with memory devices of different capacity 审中-公开
标题翻译：内存模块具有不同容量的内存设备
公开(公告)号：US20060059298A1
公开(公告)日：2006-03-16
申请号：US11102181
申请日：2005-04-08
申请人： Jeong-Hyeon Cho , Jung-Joon Lee , You-Keun Han , Byung-Se So
发明人： Jeong-Hyeon Cho , Jung-Joon Lee , You-Keun Han , Byung-Se So
IPC分类号： G06F12/00
CPC分类号： G11C5/04
摘要： A memory module includes a first set of at least one first type of memory device and a second set of at least one second type of memory device having a higher capacity than the first type. In addition, an additional capacity portion of the first and second sets stores information for an additional function of the memory module, and a remaining capacity portion of the first and second sets forms a rank of the memory module. The memory module avoids an asymmetric topology of signal lines and yet provides additional memory capacity.
摘要翻译：存储器模块包括具有比第一类型更高的容量的至少一种第一类型的存储器件的第一组和至少一种第二类型的存储器件的第二组。此外，第一组和第二组的附加容量部分存储用于存储器模块的附加功能的信息，并且第一组和第二组的剩余容量部分形成存储器模块的等级。存储器模块避免信号线的不对称拓扑，并提供额外的存储容量。

7. 发明授权

US07818488B2 Memory module with registers 有权
标题翻译：带寄存器的内存模块
公开(公告)号：US07818488B2
公开(公告)日：2010-10-19
申请号：US10975810
申请日：2004-10-27
申请人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
发明人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
IPC分类号： G06F12/00 , G06F12/06 , G06F13/00 , G06F13/28 , G11C8/00
CPC分类号： G11C5/04
摘要： Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
摘要翻译：成对的具有减少引脚的寄存器被布置成在存储器模块的前表面和后表面上重叠。输入信号INS通过寄存器以菊花链的方式串联传输，以避免输入信号INS的发散，从而保持信号完整性。每个寄存器将输入信号INS缓冲到紧靠寄存器侧面的存储体，以减少布线面积。

8. 发明申请

US20050097264A1 Memory module with registers 有权
标题翻译：带寄存器的内存模块
公开(公告)号：US20050097264A1
公开(公告)日：2005-05-05
申请号：US10975810
申请日：2004-10-27
申请人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
发明人： Kwang-Soo Park , Jeong-Hyeon Cho , Byung-Se So , Jung-Joon Lee , Young Yun , Kwang-Seop Kim
IPC分类号： G06F12/00 , G06F12/06 , G06F13/16 , G11C5/00 , H01L23/50
CPC分类号： G11C5/04
摘要： Pairs of registers with reduced pins are disposed to overlap on front and back surfaces of a memory module. An input signal INS is transferred through the registers in series in a daisy chain fashion to avoid divergence of the input signal INS for preserved signal integrity. Each register buffers the input signal INS to memory banks disposed closely to sides of the register for reduced wiring area.
摘要翻译：成对的具有减少引脚的寄存器被布置成在存储器模块的前表面和后表面上重叠。输入信号INS通过寄存器以菊花链的方式串联传输，以避免输入信号INS的发散，从而保持信号完整性。每个寄存器将输入信号INS缓冲到紧靠寄存器侧面的存储体，以减少布线面积。

9. 发明授权

US07227258B2 Mounting structure in integrated circuit module 失效
标题翻译：集成电路模块中的安装结构
公开(公告)号：US07227258B2
公开(公告)日：2007-06-05
申请号：US10988390
申请日：2004-11-12
申请人： Jeong-Hyeon Cho , Byung-Se So , Jin-Kyu Chang
发明人： Jeong-Hyeon Cho , Byung-Se So , Jin-Kyu Chang
IPC分类号： H01L23/34
CPC分类号： H05K1/181 , H01L2924/0002 , H05K2201/097 , H05K2201/10378 , H05K2201/10515 , H05K2201/10734 , Y02P70/611 , H01L2924/00
摘要： Embodiments of the present invention may include an integrated circuit module structure for a high-density mounting. An embodiment may include a wiring board, having a mounting space with a mounting length determined in a first direction and a mounting width determined in a second direction, on at least one surface thereof, and a plurality of integrated circuit packages having a package mounting combination length longer than the mounting length of the wiring board. An embodiment may also have some packages among the plurality of integrated circuit packages mounted directly on the mounting space, while other packages are mounted indirectly on the mounting space. The present embodiment may have packages that are overlapped horizontally and vertically distant from one another. Embodiments allow a plurality of chips or packages to be mounted in a limited area without changing a form factor of integrated circuit module even when integrated circuit chip or package size increases.
摘要翻译：本发明的实施例可以包括用于高密度安装的集成电路模块结构。一个实施例可以包括布线板，具有在其至少一个表面上具有在第一方向上确定的安装长度和在第二方向上确定的安装宽度的安装空间的安装空间以及具有封装安装组合的多个集成电路封装长度比布线板的安装长度长。实施例还可以在直接安装在安装空间上的多个集成电路封装中具有一些封装，而其他封装间接安装在安装空间上。本实施例可以具有水平和垂直地彼此重叠的封装。即使在集成电路芯片或封装尺寸增加时，实施例允许多个芯片或封装被安装在有限的区域中而不改变集成电路模块的外形尺寸。

10. 发明授权

US07276786B2 Stacked board-on-chip package having mirroring structure and dual inline memory module on which the stacked board-on-chip packages are mounted 失效
标题翻译：具有镜像结构和双列直插存储器模块的堆叠板上芯片封装，其上安装有堆叠板上芯片封装
公开(公告)号：US07276786B2
公开(公告)日：2007-10-02
申请号：US11177736
申请日：2005-07-08
申请人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
发明人： Jeong-Hyeon Cho , Jung-Joon Lee , Do-Hyung Kim , Byung-Se So
IPC分类号： H01L23/42 , H01L23/58 , H01L29/40
CPC分类号： H01L25/105 , H01L23/3128 , H01L25/16 , H01L2224/06136 , H01L2224/48091 , H01L2224/4824 , H01L2225/1023 , H01L2225/107 , H01L2225/1094 , H01L2924/15311 , H01L2924/15331 , H01L2924/19041 , H01L2924/00014
摘要： Embodiments of the invention include a stacked board-on-chip (BOC) package having a mirroring structure and a dual inline memory module (DIMM) on which the stacked BOC package is mounted. A bottom surface of a first semiconductor chip faces a bottom surface of a second semiconductor chip. An interposer electrically connects first and second packages, respectively comprising the first and second semiconductor chips, to each other. The DIMM is obtained by electrically connecting BOC packages to each other on upper and lower substrates of a printed circuit board. Since a height of the stacked BOC packages is greater than a height of a conventional stacked BOC package, the DIMM has a minimum stub length and an optimal topology. Hence, the DIMM can have a signal with excellent fidelity by reducing a load upon a signal line, and installation or wiring of components within the DIMM 300 requires less effort.
摘要翻译：本发明的实施例包括具有镜像结构的堆叠板上芯片（BOC）封装和其上安装有堆叠的BOC封装的双列直插存储器模块（DIMM）。第一半导体芯片的底面朝向第二半导体芯片的底面。插入器将分别包括第一和第二半导体芯片的第一和第二封装彼此电连接。通过在印刷电路板的上下基板上将BOC封装彼此电连接来获得DIMM。由于堆叠的BOC封装的高度大于常规堆叠BOC封装的高度，所以DIMM具有最小的短截线长度和最佳拓扑。因此，通过减少信号线上的负载，DIMM可以具有出色的保真度的信号，并且DIMM 300内的组件的安装或接线需要较少的努力。

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