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    • 1. 发明申请
    • MOBILE TERMINAL HAVING AN LED BACKLIGHT UNIT
    • 具有LED背光单元的移动终端
    • US20110014955A1
    • 2011-01-20
    • US12712576
    • 2010-02-25
    • Sang Joon KIMByung-Hyun Lee
    • Sang Joon KIMByung-Hyun Lee
    • G09G5/10H04W88/02G06F3/041
    • H04M1/22G02F1/133603G02F2001/133601G06F3/0488G09G3/3426G09G2320/0626G09G2320/0686G09G2330/021G09G2330/022G09G2354/00H04M2250/22
    • A mobile terminal having a display unit provided with an LED backlight and controlling method thereof are disclosed. The present invention includes a housing, a display unit including a liquid crystal display provided to one side of the housing and a backlight unit including a plurality of light emitting diodes for a backlight provided to a backside of the liquid crystal display and a control unit controlling the backlight unit to selectively adjust brightness of the light emitting diodes in part. Accordingly, a mobile terminal according to at least one of embodiments of the present invention controls light emission of an LED backlight locally, thereby providing more various display visual effects. And, a mobile terminal according to one embodiment of the present invention is able to use at least one portion of the light emitted from an LED BLU of a display unit as an illumination of a main body without using a separate light source for external illumination. Moreover, the illumination of the main body is able to play a role as a transmitter in a visible light communication.
    • 公开了具有设置有LED背光的显示单元的移动终端及其控制方法。 本发明包括壳体,包括设置在壳体一侧的液晶显示器的显示单元和设置在液晶显示器背面的用于背光源的多个发光二极管的背光单元,以及控制单元, 背光单元部分地选择性地调节发光二极管的亮度。 因此,根据本发明的实施例的至少一个的移动终端本地控制LED背光的发光,从而提供更多种不同的显示视觉效果。 并且,根据本发明的一个实施例的移动终端能够使用从显示单元的LED BLU发射的光的至少一部分作为主体的照明,而不使用用于外部照明的单独的光源。 此外,主体的照明能够在可见光通信中起到发射器的作用。
    • 4. 发明申请
    • Recombinant Expression Vector for Production of Plants Having Multiple Stress Tolerances, and Method for Preparing Multiple Stress-Tolerant Plants Using the Same
    • 用于生产具有多重胁迫耐受性的植物的重组表达载体,以及使用该多重胁迫耐受植物的多个耐胁迫植物的制备方法
    • US20080244792A1
    • 2008-10-02
    • US11718661
    • 2005-01-28
    • Sang-Soo KwakSuk-Yoon KwonHaeng-Soon LeeLi TangSoon LimByung-Hyun Lee
    • Sang-Soo KwakSuk-Yoon KwonHaeng-Soon LeeLi TangSoon LimByung-Hyun Lee
    • C12N15/63A01H5/00C12N15/87
    • C12N9/0065C12N9/0089C12N15/8271C12N15/8273C12N15/895
    • The present invention relates to a recombinant expression vector for production of multiple stress tolerant plants, which is prepared by attaching multiple stress tolerant genes to oxidative stress inducible promoter, multiple stress tolerant plants transformed with the expression vector and a preparation method for the plants, more precisely, a recombinant expression vector for production of multiple stress tolerant plants that is prepared by combining oxidative stress inducible peroxidase promoter (SWPA2) originated from sweetpotato with multiple stress tolerant genes (SOD (superoxide dismutase) and APX (ascobate peroxidase)) to express the multiple stress tolerant genes in chloroplasts, multiple stress tolerant plants transformed with the expression vector above and a preparation method for the plants. The recombinant expression vector of the present invention is very useful for the production of transformed plants having very strong resistance against multiple stresses caused by oxidative stress inducible herbicides, cold injury, high temperature, salt damage, or various environmental pollutions generating active oxygen, so that the vector can be a great contribution to the increase of productivity of agricultural crops or mass-production of useful components.
    • 本发明涉及用于产生多种胁迫耐受植物的重组表达载体,其通过将多个胁迫耐受基因连接到氧化应激诱导型启动子,用表达载体转化的多种胁迫耐受植物和植物的制备方法 准确地说,通过将源自甘薯的氧化应激诱导型过氧化物酶启动子(SWPA2)与多重胁迫耐受基因(SOD(超氧化物歧化酶)和APX(ascobate过氧化物酶))组合来制备多重胁迫耐受植物的重组表达载体,以表达 叶绿体中的多重胁迫耐受基因,用上述表达载体转化的多种胁迫耐受植物和植物的制备方法。 本发明的重组表达载体对于生产对由氧化应激诱导型除草剂,冷伤害,高温,盐损害或产生活性氧的各种环境污染引起的多重胁迫具有非常强的抗性的转化植物的生产非常有用,使得 该载体可以为提高农作物生产力或大量生产有用成分做出重大贡献。
    • 5. 发明授权
    • Memory device and method of operating the same
    • 存储器件及其操作方法
    • US09069694B2
    • 2015-06-30
    • US13610996
    • 2012-09-12
    • Byung-Hyun Lee
    • Byung-Hyun Lee
    • G06F11/00G06F11/10H03M13/09
    • G06F11/1004H03M13/091
    • A method for operating a memory device is disclosed. The method includes receiving a serial data and a serial cyclic redundancy check (CRC) code transmitted sequentially through a channel, converting the serial data into a parallel data and the serial CRC code into a parallel CRC code, outputting the parallel data at a first time point, outputting the parallel CRC code at a second time point later than the first time point, calculating a CRC code by using the parallel data, comparing the parallel CRC code and the calculated CRC code with each other and detecting an error of the serial data transmitted through the channel according to the result of the comparison, and outputting an error detection signal in response to the result of the comparison.
    • 公开了一种用于操作存储器件的方法。 该方法包括接收通过信道顺序发送的串行数据和串行循环冗余校验(CRC)码,将串行数据转换为并行数据,并将串行CRC码转换成并行CRC码,第一次输出并行数据 点,在比第一时间点晚的第二时间点输出并行CRC码,通过使用并行数据计算CRC码,将并行CRC码和计算出的CRC码进行比较,并检测串行数据的错误 根据比较结果通过信道发送,并且响应于比较结果输出错误检测信号。
    • 6. 发明申请
    • Semiconductor memory device
    • 半导体存储器件
    • US20100226187A1
    • 2010-09-09
    • US12660439
    • 2010-02-26
    • Byung-Hyun LeeByung-Sik MoonSeung-Bum Ko
    • Byung-Hyun LeeByung-Sik MoonSeung-Bum Ko
    • G11C7/00G11C8/08G11C5/14
    • G11C7/18G11C11/4087G11C2207/002
    • A semiconductor memory device includes a memory cell array having a plurality of memory cells coupled between a plurality of word lines and a plurality of bit line pairs, a bit line selection circuit configured to transmit data between a selected bit line pair and a local input/output line pair in response to a column selection signal, a local global input/output gate circuit configured to transmit data between the local input/output line pair and a global input/output line pair in response to a local global input/output selection signal, and a controller configured to drive the word lines, output the column selection signal having a first voltage level to the bit line selection circuit, and output the local global input/output selection signal having a second voltage level that is lower than the first voltage level to the local global input/output gate circuit, in response to an external address signal and an external command.
    • 半导体存储器件包括存储单元阵列,该存储单元阵列具有耦合在多个字线和多个位线对之间的多个存储器单元,位线选择电路被配置为在所选择的位线对和本地输入/ 响应于列选择信号的输出线对;本地全局输入/输出门电路,被配置为响应于局部全局输入/输出选择信号在本地输入/输出线对与全局输入/输出线对之间传输数据 以及控制器,被配置为驱动字线,将具有第一电压电平的列选择信号输出到位线选择电路,并输出具有低于第一电压的第二电压电平的局部全局输入/输出选择信号 响应于外部地址信号和外部命令,电平到本地全局输入/输出门电路。
    • 8. 发明申请
    • METHOD OF FABRICATING SEMICONDUCTOR DEVICE HAVING ALIGNMENT KEY AND SEMICONDUCTOR DEVICE FABRICATED THEREBY
    • 具有对准键的半导体器件的制造方法及其制造的半导体器件
    • US20090087962A1
    • 2009-04-02
    • US12325694
    • 2008-12-01
    • Min-Hee ChoYoo-Sang HwangByung-Hyun Lee
    • Min-Hee ChoYoo-Sang HwangByung-Hyun Lee
    • H01L21/02
    • H01L27/10894H01L23/544H01L27/10814H01L28/91H01L2223/54426H01L2223/54453H01L2223/5446H01L2924/0002H01L2924/00
    • In a method of fabricating a semiconductor device having an alignment key and a semiconductor device fabricated thereby. The method of fabricating a semiconductor device includes providing a semiconductor substrate having a scribe lane region and a cell region. An etch barrier pattern and a gate pattern are formed on the scribe lane region and the cell region respectively. A first interlayer insulating layer is formed to cover the etch barrier pattern and the gate pattern. A preliminary alignment key pattern and a bit line pattern are formed on the first interlayer insulating layer of the scribe lane region and the cell region respectively. A second interlayer insulating layer is formed to cover the preliminary alignment key pattern and the bit line pattern. The second interlayer insulating layer and the first interlayer insulating layer are patterned to expose the etch barrier pattern, thereby forming an alignment key pattern in the scribe lane region, and concurrently, forming a storage node contact opening in the cell region.
    • 在制造具有对准键和由此制造的半导体器件的半导体器件的方法中。 制造半导体器件的方法包括提供具有划线通道区域和单元区域的半导体衬底。 蚀刻阻挡图案和栅极图案分别形成在划线路区域和单元区域上。 形成第一层间绝缘层以覆盖蚀刻阻挡图案和栅极图案。 分别在划线路区域和单元区域的第一层间绝缘层上形成初步对准键图案和位线图案。 形成第二层间绝缘层以覆盖初步对准键图案和位线图案。 将第二层间绝缘层和第一层间绝缘层图案化以暴露蚀刻阻挡图案,从而在划线路区域中形成对准键图案,同时在单元区域中形成存储节点接触开口。