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1. 发明授权

US09035396B2 Semiconductor device including dummy gate part and method of fabricating the same 有权
公开(公告)号：US09035396B2
公开(公告)日：2015-05-19
申请号：US13240475
申请日：2011-09-22
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L27/14 , H01L29/76 , H01L21/3105 , H01L27/105 , H01L29/66
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.

2. 发明授权

US08053845B2 Semiconductor device including dummy gate part and method of fabricating the same 有权
标题翻译：半导体器件包括伪栅极部分及其制造方法
公开(公告)号：US08053845B2
公开(公告)日：2011-11-08
申请号：US12291211
申请日：2008-11-07
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L21/70
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要翻译：在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

3. 发明申请

US20090121296A1 Semiconductor device including dummy gate part and method of fabricating the same 有权
标题翻译：半导体器件包括伪栅极部分及其制造方法
公开(公告)号：US20090121296A1
公开(公告)日：2009-05-14
申请号：US12291211
申请日：2008-11-07
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L27/10
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要翻译：在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

4. 发明申请

US20120028435A1 SEMICONDUCTOR DEVICE INCLUDING DUMMY GATE PART AND METHOD OF FABRICATING THE SAME 审中-公开
标题翻译：包括双门部分的半导体器件及其制造方法
公开(公告)号：US20120028435A1
公开(公告)日：2012-02-02
申请号：US13240475
申请日：2011-09-22
申请人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
发明人： Byoung-ho Kwon , Sang-youn Jo , Jin-sook Choi , Chang-ki Hong , Bo-un Yoon , Hong-soo Kim , Se-rah Yun
IPC分类号： H01L21/76
CPC分类号： H01L21/31053 , H01L27/105 , H01L27/1052 , H01L29/66545
摘要： In a reliable semiconductor device and a method of fabricating the semiconductor device, a difference in height between upper surfaces of a cell region and a peripheral region (also referred to as a level difference) is minimized by optimizing dummy gate parts. The semiconductor device includes a semiconductor substrate including a cell region and a peripheral region surrounding the cell region, a plurality of dummy active regions surrounded by a device isolating region and formed apart from each other, and a plurality of dummy gate parts formed on the dummy active regions and on the device isolating regions located between the dummy active regions, wherein each of the dummy gate parts covers two or more of the dummy active regions.
摘要翻译：在可靠的半导体器件和制造半导体器件的方法中，通过优化虚拟栅极部分来最小化单元区域的上表面与外围区域之间的高度差（也称为电平差）。半导体器件包括：半导体衬底，包括单元区域和围绕单元区域的周边区域;多个虚设有源区域，被器件隔离区域包围并形成为彼此分离;多个虚拟栅极部件，形成在虚拟区域上; 有源区域和位于虚拟有源区域之间的器件隔离区域，其中每个伪栅极部分覆盖两个或更多个虚拟有源区域。

5. 发明授权

US08227354B2 Method of forming semiconductor device patterns 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US08227354B2
公开(公告)日：2012-07-24
申请号：US12480807
申请日：2009-06-09
申请人： Bong-cheol Kim , Dae-youp Lee , Sang-youn Jo , Ja-min Koo , Byeong-hwan Son , Jang-hwan Jeong
发明人： Bong-cheol Kim , Dae-youp Lee , Sang-youn Jo , Ja-min Koo , Byeong-hwan Son , Jang-hwan Jeong
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/32139 , H01L27/11521
摘要： Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.
摘要翻译：提供了一种形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且通过在半导体器件的一部分中的双重图案化工艺可以使图案密度加倍。在形成半导体器件的图案的方法中，在衬底上形成具有不同宽度的第一模具掩模图案和第二模具掩模图案。形成覆盖第一模具掩模图案的两个侧壁的一对第一间隔件和覆盖第二模具掩模图案的两个侧壁的一对第二间隔件。去除第一模具掩模图案和第二模具掩模图案，并且形成覆盖第二间隔件的宽幅掩模图案。使用第一间隔物，第二间隔物和宽幅掩模图案作为蚀刻掩模蚀刻下层。

6. 发明申请

US20100173492A1 METHOD OF FORMING SEMICONDUCTOR DEVICE PATTERNS 有权
标题翻译：形成半导体器件图案的方法
公开(公告)号：US20100173492A1
公开(公告)日：2010-07-08
申请号：US12480807
申请日：2009-06-09
申请人： Bong-cheol Kim , Dae-youp Lee , Sang-youn Jo , Ja-min Koo , Byeong-hwan Son , Jang-hwan Jeong
发明人： Bong-cheol Kim , Dae-youp Lee , Sang-youn Jo , Ja-min Koo , Byeong-hwan Son , Jang-hwan Jeong
IPC分类号： H01L21/308
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/32139 , H01L27/11521
摘要： Provided is a method of forming patterns of a semiconductor device, whereby patterns having various widths can be simultaneously formed, and pattern density can be doubled by a double patterning process in a portion of the semiconductor device. In the method of forming patterns of a semiconductor device, a first mold mask pattern and a second mold mask patter having different widths are formed on a substrate. A pair of first spacers covering both sidewalls of the first mold mask pattern and a pair of second spacers covering both sidewalls of the second mold mask pattern are formed. The first mold mask pattern and the second mold mask pattern are removed, and a wide-width mask pattern covering the second spacer is formed. A lower layer is etched using the first spacers, the second spacers, and the wide-width mask pattern as an etch mask.
摘要翻译：提供了一种形成半导体器件的图案的方法，由此可以同时形成具有各种宽度的图案，并且通过在半导体器件的一部分中的双重图案化工艺可以使图案密度加倍。在形成半导体器件的图案的方法中，在衬底上形成具有不同宽度的第一模具掩模图案和第二模具掩模图案。形成覆盖第一模具掩模图案的两个侧壁的一对第一间隔件和覆盖第二模具掩模图案的两个侧壁的一对第二间隔件。去除第一模具掩模图案和第二模具掩模图案，并且形成覆盖第二间隔件的宽幅掩模图案。使用第一间隔物，第二间隔物和宽幅掩模图案作为蚀刻掩模蚀刻下层。

7. 发明授权

US07920021B2 Method of applying wire voltage to semiconductor device 有权
标题翻译：将线电压施加到半导体器件的方法
公开(公告)号：US07920021B2
公开(公告)日：2011-04-05
申请号：US12580299
申请日：2009-10-16
申请人： Jin-Yong Oh , Sang-youn Jo , Joon-hee Lee , Jae-sun Yun , Seong-soo Kim
发明人： Jin-Yong Oh , Sang-youn Jo , Joon-hee Lee , Jae-sun Yun , Seong-soo Kim
IPC分类号： H01L25/00
CPC分类号： G11C16/10
摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.
摘要翻译：一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上，多根电线。因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

8. 发明申请

US20100207690A1 METHOD OF APPLYING WIRE VOLTAGE TO SEMICONDUCTOR DEVICE 有权
标题翻译：将电压施加到半导体器件的方法
公开(公告)号：US20100207690A1
公开(公告)日：2010-08-19
申请号：US12580299
申请日：2009-10-16
申请人： Jin-Yong Oh , Sang-youn Jo , Joon-hee Lee , Jae-sun Yun , Seong-soo Kim
发明人： Jin-Yong Oh , Sang-youn Jo , Joon-hee Lee , Jae-sun Yun , Seong-soo Kim
IPC分类号： H03H11/24 , H03F3/14
CPC分类号： G11C16/10
摘要： A method of applying a wire voltage to a semiconductor device including a plurality of active regions and a field region insulating the plurality of active regions, wherein the field region includes a plurality of wires. The method includes applying an operating voltage required for an operation of the semiconductor device to at least one of the plurality of wires, and applying a voltage lower than the operating voltage to a wire adjacent to at least one of the plurality of active regions from among the plurality of wires. Thus, leakage current caused by an imaginary parasitic transistor due to a wire of the field region may be prevented.
摘要翻译：一种将线电压施加到包括多个有源区的半导体器件和使多个有源区绝缘的场区的方法，其中所述场区包括多根线。该方法包括将半导体器件的操作所需的工作电压施加到多根导线中的至少一根，并将低于工作电压的电压施加到与多个有源区中的至少一个相邻的导线上，多根电线。因此，可以防止由于场区域的导线引起的由虚拟寄生晶体管引起的漏电流。

9. 发明授权

US5750433A Methods of forming electrically isolated active region pedestals using trench-based isolation techniques 失效
标题翻译：使用基于沟槽的隔离技术形成电隔离的有源区域基座的方法
公开(公告)号：US5750433A
公开(公告)日：1998-05-12
申请号：US748865
申请日：1996-11-14
申请人： Sang-youn Jo
发明人： Sang-youn Jo
IPC分类号： H01L21/66 , H01L21/76 , H01L21/762 , H01L21/8242 , H01L27/108
CPC分类号： H01L21/76224
摘要： Methods of forming electrically isolated active regions in semiconductor substrates include the steps of forming a plurality of trenches in a face of a semiconductor substrate to define an active region pedestal between first and second dummy region pedestals and then forming an electrically insulating layer on the active region and dummy region pedestals and in the trenches disposed therebetween. A mask is then patterned to expose a portion of the electrically insulating layer on the active region pedestal and then the exposed portion of the electrically insulating layer is etched so that a thickness of the electrically insulating layer on the active region pedestal is less than a thickness of the electrically insulating layer on the first and second dummy region pedestals. A step is then performed to planarize the electrically insulating layer to selectively expose the active region pedestal but not the first and second dummy region pedestals. This planarizing step also results in the formation of a uniform surface profile at the edges of the active region pedestal.
摘要翻译：在半导体衬底中形成电绝缘的有源区的方法包括以下步骤：在半导体衬底的表面上形成多个沟槽，以在第一和第二虚拟区域基座之间限定有源区基座，然后在有源区上形成电绝缘层和虚设区域基座，并设置在它们之间的沟槽中。然后对掩模进行构图以暴露有源区基座上的电绝缘层的一部分，然后蚀刻电绝缘层的暴露部分，使得有源区基座上的电绝缘层的厚度小于厚度在第一和第二虚拟区域基座上的电绝缘层。然后执行步骤以使电绝缘层平坦化以选择性地暴露有源区基座，而不是第一和第二虚拟区基座。该平坦化步骤还导致在有源区基座的边缘处形成均匀的表面轮廓。

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