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1. 发明申请

US20050023634A1 Method of fabricating shallow trench isolation structure and microelectronic device having the structure 审中-公开
标题翻译：制造浅沟槽隔离结构的方法和具有该结构的微电子器件
公开(公告)号：US20050023634A1
公开(公告)日：2005-02-03
申请号：US10862336
申请日：2004-06-08
申请人： Byoung-Moon Yoon , Min-Jin Lee , Yong-Sun Ko , In-Seak Hwang , Won-Jun Lee
发明人： Byoung-Moon Yoon , Min-Jin Lee , Yong-Sun Ko , In-Seak Hwang , Won-Jun Lee
IPC分类号： H01L21/762 , H01L21/763 , H01L21/76 , H01L29/00
CPC分类号： H01L21/763 , H01L21/76224
摘要： Provided is a method of fabricating a shallow trench isolation (STI) structure having a high aspect ratio and improved insulating properties. The exemplary method includes filling a shallow trench isolation region opening with an undoped polysilicon layer, removing an upper portion of the undoped polysilicon layer to form a second opening having a reduced aspect ratio relative to the original opening and filling the second opening with an insulating material to complete the STI structure. Additional protective layers including silicon oxide, silicon nitride and/or a capping layer may be provided on the sidewalls of the opening before depositing the undoped polysilicon.
摘要翻译：提供一种制造具有高纵横比和改进的绝缘性能的浅沟槽隔离（STI）结构的方法。该示例性方法包括填充具有未掺杂多晶硅层的浅沟槽隔离区开口，去除未掺杂多晶硅层的上部，以形成相对于原始开口具有减小的纵横比的第二开口，并用绝缘材料填充第二开口完成STI结构。在沉积未掺杂的多晶硅之前，可以在开口的侧壁上提供包括氧化硅，氮化硅和/或覆盖层的附加保护层。

2. 发明授权

US07338610B2 Etching method for manufacturing semiconductor device 失效
标题翻译：蚀刻方法制造半导体器件
公开(公告)号：US07338610B2
公开(公告)日：2008-03-04
申请号：US10763356
申请日：2004-01-23
申请人： Won-Jun Lee , Byoung-Moon Yoon , In-Seak Hwang , Yong-Sun Ko
发明人： Won-Jun Lee , Byoung-Moon Yoon , In-Seak Hwang , Yong-Sun Ko
IPC分类号： H01L21/302 , H01L21/461
CPC分类号： H01L28/91 , H01L21/31111
摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
摘要翻译：提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。用诸如LAL的化学溶液蚀刻电介质层。在蚀刻之前，电极的突出部分被去除或减少，以防止化学溶液中包含的任何气泡粘附到电极上。因此，化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

3. 发明申请

US20050064674A1 Etching method for manufacturing semiconductor device 失效
标题翻译：蚀刻方法制造半导体器件
公开(公告)号：US20050064674A1
公开(公告)日：2005-03-24
申请号：US10763356
申请日：2004-01-23
申请人： Won-Jun Lee , Byoung -Moon Yoon , In-Seak Hwang , Yong-Sun Ko
发明人： Won-Jun Lee , Byoung -Moon Yoon , In-Seak Hwang , Yong-Sun Ko
IPC分类号： H01L27/108 , H01L21/02 , H01L21/311 , H01L21/20 , H01L21/302 , H01L21/461
CPC分类号： H01L28/91 , H01L21/31111
摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. The dielectric layer is etched with a chemical solution such as LAL. Prior to etching, the protruding portion of the electrode is removed or reduced to prevent any bubbles included in the chemical solution from adhering to the electrode. Thus, the chemical solution can etch the dielectric layers without being blocked by any bubbles included in a chemical solution.
摘要翻译：提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。用诸如LAL的化学溶液蚀刻电介质层。在蚀刻之前，电极的突出部分被去除或减少，以防止化学溶液中包含的任何气泡粘附到电极上。因此，化学溶液可以蚀刻介电层而不被包含在化学溶液中的任何气泡所阻挡。

4. 发明申请

US20050026452A1 Etching method for manufacturing semiconductor device 审中-公开
标题翻译：蚀刻方法制造半导体器件
公开(公告)号：US20050026452A1
公开(公告)日：2005-02-03
申请号：US10855313
申请日：2004-05-26
申请人： Won-Jun Lee , Byoung-Moon Yoon , In-Seak Hwang , Yong-Sun Ko
发明人： Won-Jun Lee , Byoung-Moon Yoon , In-Seak Hwang , Yong-Sun Ko
IPC分类号： H01L21/02 , H01L21/311 , H01L21/8242 , H01L21/302 , H01L21/461
CPC分类号： H01L28/91 , H01L21/31111 , H01L27/10852
摘要： A wafer having a dielectric layer and an electrode partially protruding from the top surface of the dielectric layer is provided. An etchant or chemical solution is applied to the dielectric layer and bubbles in the etchant are prevented from adhering to the electrode. In one embodiment, prior to etching, the protruding portion is covered with a buffer layer to prevent bubbles in the etchant from adhering to the electrode. Thus, the etchant can etch the dielectric layers without being blocked by bubbles included therein.
摘要翻译：提供具有电介质层和从电介质层的顶表面部分突出的电极的晶片。将蚀刻剂或化学溶液施加到电介质层，并且防止蚀刻剂中的气泡粘附到电极上。在一个实施例中，在蚀刻之前，突出部分被缓冲层覆盖，以防止蚀刻剂中的气泡粘附到电极上。因此，蚀刻剂可以蚀刻电介质层而不被其中包含的气泡阻挡。

5. 发明申请

US20080214006A1 METHODS OF USING CORROSION-INHIBITING CLEANING COMPOSITIONS FOR METAL LAYERS AND PATTERNS ON SEMICONDUCTOR SUBSTRATES 审中-公开
标题翻译：在金属层上使用腐蚀抑制性清洁组合物和在半导体衬底上形成图案的方法
公开(公告)号：US20080214006A1
公开(公告)日：2008-09-04
申请号：US12122264
申请日：2008-05-16
申请人： Kwang-Wook Lee , In-Seak Hwang , Yong-Sun Ko , Byoung-Moon Yoon , Kyung-Hyun Kim , Ky-Sub Kim , Sun-Young Song , Hyuk-Jin Lee , Byung-Mook Kim
发明人： Kwang-Wook Lee , In-Seak Hwang , Yong-Sun Ko , Byoung-Moon Yoon , Kyung-Hyun Kim , Ky-Sub Kim , Sun-Young Song , Hyuk-Jin Lee , Byung-Mook Kim
IPC分类号： H01L21/461 , G03C1/00
CPC分类号： H01L21/02071 , C11D3/0073 , C11D3/042 , C11D3/046 , C11D3/2082 , C11D3/30 , C11D3/364 , C11D3/39 , C11D3/3947 , C11D11/0047 , C23G1/106
摘要： Provided herein are methods for using corrosion-inhibiting cleaning compositions for semiconductor wafer processing that include an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant.
摘要翻译：本文提供了使用用于半导体晶片加工的腐蚀抑制清洁组合物的方法，其包括至少水，表面活性剂和选自氨基膦酸盐，多胺和多元羧酸的腐蚀抑制化合物的水性混合物。混合物中腐蚀抑制化合物的量优选在约0.0001重量％至约0.1重量％的范围内，表面活性剂的量优选在约0.001重量％至约1.0重量％的范围内。水性混合物还可以包括作为氧化物蚀刻剂的硫酸和氟化物，以及充当金属蚀刻剂的过氧化物。

6. 发明授权

US06831012B2 Method for forming a silicide film of a semiconductor device 有权
标题翻译：用于形成半导体器件的硅化物膜的方法
公开(公告)号：US06831012B2
公开(公告)日：2004-12-14
申请号：US10445858
申请日：2003-05-28
申请人： Dae-Keun Kang , Yong-Sun Ko , In-Seak Hwang , Byoung-Moon Yoon
发明人： Dae-Keun Kang , Yong-Sun Ko , In-Seak Hwang , Byoung-Moon Yoon
IPC分类号： H01L2144
CPC分类号： H01L21/823443 , H01L21/02063 , H01L21/31111 , H01L21/823425 , H01L27/10888 , H01L27/10891 , H01L27/10894 , H01L29/665
摘要： After a silicidation blocking pattern is formed on a substrate including silicon, the silicidation blocking pattern is hardened by a thermal annealing process. The substrate is rinsed to remove a native oxide film formed on the substrate, and then a silicide film is formed on a portion of the substrate exposed by the silicidation blocking pattern. The silicide film can thus be formed in an exact portion of the substrate, and the substrate is not damaged during rinsing.
摘要翻译：在包含硅的衬底上形成硅化阻挡图案之后，通过热退火工艺使硅化阻挡图案硬化。冲洗衬底以去除在衬底上形成的自然氧化膜，然后在通过硅化阻挡图案暴露的衬底的一部分上形成硅化物膜。因此，硅化物膜可以形成在衬底的精确部分中，并且衬底在漂洗期间不被损坏。

7. 发明申请

US20050176604A1 Corrosion-inhibiting cleaning compositions for metal layers and patterns on semiconductor substrates 审中-公开
标题翻译：用于金属层和半导体衬底上的图案的防腐蚀清洁组合物
公开(公告)号：US20050176604A1
公开(公告)日：2005-08-11
申请号：US11021040
申请日：2004-12-23
申请人： Kwang-Wook Lee , In-Seak Hwang , Yong-Sun Ko , Byoung-Moon Yoon , Kyung-Hyun Kim , Ky-Sub Kim , Sun-Young Song , Hyuk-Jin Lee , Byung-Mook Kim
发明人： Kwang-Wook Lee , In-Seak Hwang , Yong-Sun Ko , Byoung-Moon Yoon , Kyung-Hyun Kim , Ky-Sub Kim , Sun-Young Song , Hyuk-Jin Lee , Byung-Mook Kim
IPC分类号： C11D1/722 , C09K13/04 , C09K13/08 , C11D1/00 , C11D3/02 , C11D3/04 , C11D3/20 , C11D3/30 , C11D3/36 , C11D3/39 , C11D11/00 , C11D17/08 , C23G5/036 , H01L21/02 , H01L21/28 , H01L21/30 , H01L21/302 , H01L21/304 , H01L21/321 , H01L21/3213 , H01L21/82 , H01L21/8239 , H01L21/8242 , H01L27/108 , H01L29/78
CPC分类号： H01L21/02071 , C11D3/0073 , C11D3/042 , C11D3/046 , C11D3/2082 , C11D3/30 , C11D3/364 , C11D3/39 , C11D3/3947 , C11D11/0047 , C23G1/106
摘要： A corrosion-inhibiting cleaning composition for semiconductor wafer processing includes an aqueous admixture of at least water, a surfactant and a corrosion-inhibiting compound selected from a group consisting of amino phosphonates, polyamines and polycarboxylic acids. The quantity of the corrosion-inhibiting compound in the admixture is preferably in a range from about 0.0001 wt % to about 0.1 wt % and the quantity of the surfactant is preferably in a range from about 0.001 wt % to about 1.0 wt %. The aqueous admixture may also include sulfuric acid and a fluoride, which act as oxide etchants, and a peroxide, which acts as a metal etchant.
摘要翻译：用于半导体晶片处理的腐蚀抑制清洁组合物包括至少水，表面活性剂和选自氨基膦酸盐，多胺和多元羧酸的腐蚀抑制化合物的水性混合物。混合物中腐蚀抑制化合物的量优选在约0.0001重量％至约0.1重量％的范围内，表面活性剂的量优选在约0.001重量％至约1.0重量％的范围内。水性混合物还可以包括作为氧化物蚀刻剂的硫酸和氟化物，以及充当金属蚀刻剂的过氧化物。

8. 发明授权

US06946431B2 Cleaning solution including aqueous ammonia solution, acetic acid and deionized water for integrated circuit devices and methods of cleaning integrated circuit devices using the same 有权
标题翻译：包括用于集成电路器件的氨水溶液，乙酸和去离子水的清洗溶液以及使用其的集成电路器件的清洁方法
公开(公告)号：US06946431B2
公开(公告)日：2005-09-20
申请号：US10655421
申请日：2003-09-04
申请人： In-Joon Yeo , Yong-Sun Ko , In-Seak Hwang , Byoung-Moon Yoon , Dae-Hyuk Chung , Kyung-Hyun Kim
发明人： In-Joon Yeo , Yong-Sun Ko , In-Seak Hwang , Byoung-Moon Yoon , Dae-Hyuk Chung , Kyung-Hyun Kim
IPC分类号： H01L21/304 , C11D7/06 , C11D7/26 , C11D11/00 , H01L21/302
CPC分类号： C11D11/0047 , C11D7/06 , C11D7/265
摘要： Cleaning solutions for integrated circuit devices and methods of cleaning integrated circuit devices using the same are disclosed. The cleaning solution includes about 30% aqueous ammonia solution, acetic acid by a volume percent higher then a volume percent of the aqueous ammonia solution, and deionized water by a volume percent higher then the volume percent of the acetic acid. Additionally, disclosed are methods wherein the cleaning solution is formed on integrated circuit substrates having an exposed metal pattern formed thereon, and further providing mega-sonic energy to the film of the cleaning solution.
摘要翻译：公开了用于集成电路器件的清洁解决方案和使用其的集成电路器件的清洁方法。清洗溶液包括约30％氨水溶液，乙酸的体积百分数高于氨水溶液的体积百分比，去离子水的体积百分数高于乙酸的体积百分数。此外，公开了一种方法，其中清洁溶液形成在其上形成有暴露的金属图案的集成电路基板上，并且还向清洗溶液的膜提供大的声能。

9. 发明授权

US07445997B2 Methods of forming non-volatile memory devices having floating gate electrodes 失效
标题翻译：形成具有浮动栅电极的非易失性存储器件的方法
公开(公告)号：US07445997B2
公开(公告)日：2008-11-04
申请号：US11103069
申请日：2005-04-11
申请人： Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
发明人： Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
IPC分类号： H01L21/336
CPC分类号： H01L27/115 , H01L27/11521
摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.
摘要翻译：形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。然后执行另一蚀刻步骤。该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

10. 发明申请

US20050255654A1 Methods of forming non-volatile memory devices having floating gate electrodes 失效
标题翻译：形成具有浮动栅电极的非易失性存储器件的方法
公开(公告)号：US20050255654A1
公开(公告)日：2005-11-17
申请号：US11103069
申请日：2005-04-11
申请人： Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
发明人： Won-Jun Lee , Tae-Hyun Kim , Yong-Sun Ko , Kyung-Hyun Kim , Byoung-Moon Yoon , Ji-Hong Kim
IPC分类号： H01L21/336 , H01L21/8247 , H01L27/115
CPC分类号： H01L27/115 , H01L27/11521
摘要： Methods of forming non-volatile memory devices include the steps of forming a semiconductor substrate having first and second floating gate electrodes thereon and an electrically insulating region extending between the first and second floating gate electrodes. A step is then performed to etch back the electrically insulating region to expose upper corners of the first and second floating gate electrodes. Another etching step is then performed. This etching step includes exposing upper surfaces and the exposed upper corners of the first and second floating gate electrodes to an etchant that rounds the exposed upper corners of the first and second floating gate electrodes. The step of etching back the electrically insulating region includes etching back the electrically insulating region to expose sidewalls of the first and second floating gate electrodes having heights ranging from about 30 Å to about 200 Å. The step of exposing the upper corners of the first and second floating gate electrodes to an etchant is followed by the step of etching back the electrically insulating region to expose entire sidewalls of the first and second floating gate electrodes.
摘要翻译：形成非易失性存储器件的方法包括以下步骤：在其上形成具有第一和第二浮栅的半导体衬底和在第一和第二浮栅之间延伸的电绝缘区。然后执行步骤以回蚀电绝缘区域以暴露第一和第二浮栅电极的上角。然后执行另一蚀刻步骤。该蚀刻步骤包括将第一和第二浮栅电极的上表面和暴露的上角露出到蚀刻剂，该蚀刻剂围绕第一和第二浮栅的暴露的上角。蚀刻回电绝缘区域的步骤包括蚀刻电绝缘区域以暴露第一和第二浮栅电极的侧壁，其高度范围为约至约200。将第一和第二浮栅的上角暴露于蚀刻剂的步骤之后是蚀刻电绝缘区以暴露第一和第二浮栅的整个侧壁的步骤。

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