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1. 发明授权

US08916926B2 Nonvolatile memory device and method of making the same 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US08916926B2
公开(公告)日：2014-12-23
申请号：US13310407
申请日：2011-12-02
申请人： Byeong-In Choe , Sunil Shim , Sung-Hwan Jang , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Sung-Hwan Jang , Woonkyung Lee , Jaehoon Jang
IPC分类号： H01L27/115 , G11C16/04 , H01L29/792
CPC分类号： H01L27/1157 , G11C16/0483 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.
摘要翻译：非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及介于导电材料层和支柱之间的信息存储膜。在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

2. 发明申请

US20120140562A1 NONVOLATILE MEMORY DEVICE AND METHOD OF MAKING THE SAME 有权
标题翻译：非易失存储器件及其制造方法
公开(公告)号：US20120140562A1
公开(公告)日：2012-06-07
申请号：US13310407
申请日：2011-12-02
申请人： Byeong-In Choe , Sunil Shim , Sung-Hwan Jang , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Sung-Hwan Jang , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C16/04 , H01L29/78
CPC分类号： H01L27/1157 , G11C16/0483 , H01L27/11582 , H01L29/7926
摘要： A nonvolatile memory device includes a substrate, a structure including a stack of alternately disposed layers of conductive and insulation materials disposed on the substrate, a plurality of pillars extending through the structure in a direction perpendicular to the substrate and into contact with the substrate, and information storage films interposed between the layers of conductive material and the pillars. In one embodiment, upper portions of the pillars located at the same level as an upper layer of the conductive material have structures that are different from lower portions of the pillars. In another embodiment, or in addition, upper string selection transistors constituted by portions of the pillars at the level of an upper layer of the conductive material are programmed differently from lower string selection transistors.
摘要翻译：非易失性存储器件包括衬底，包括布置在衬底上的交替设置的导电和绝缘材料层的堆叠的结构，沿与衬底垂直的方向延伸并与衬底接触的多个柱，以及介于导电材料层和支柱之间的信息存储膜。在一个实施例中，位于与导电材料的上层相同水平的柱的上部具有与柱的下部不同的结构。在另一个实施例中，或者另外，由导电材料的上层的电平的柱的部分构成的上部串选择晶体管被编程为与下部串选择晶体管不同。

3. 发明授权

US08576629B2 Operating method of nonvolatile memory device 有权
标题翻译：非易失性存储器件的操作方法
公开(公告)号：US08576629B2
公开(公告)日：2013-11-05
申请号：US13315523
申请日：2011-12-09
申请人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
发明人： Byeong-In Choe , Sunil Shim , Woonkyung Lee , Jaehoon Jang
IPC分类号： G11C11/34
CPC分类号： G11C16/10 , G11C16/0483 , G11C16/3459 , H01L27/11582
摘要： Disclosed is an operating method of a nonvolatile memory device, which includes programming the first selection transistors of the plurality of cell strings and programming the plurality of memory cells of the plurality of cell strings. The programming the first selection transistors comprises supplying a first voltage to a first bit line connected with a first selection transistor to be programmed and a different second voltage to a second bit line connected to a first selection transistor to be program inhibited; turning on the second selection transistors of the plurality of cell strings, and supplying a first program voltage to a selected first selection line among a plurality of first selection lines connected with the first selection transistors and a third voltage to an unselected first selection line among the plurality of first selection lines.
摘要翻译：公开了一种非易失性存储器件的操作方法，其包括编程多个单元串中的第一选择晶体管并对多个单元串中的多个存储单元进行编程。对第一选择晶体管进行编程包括将第一电压提供给与待编程的第一选择晶体管连接的第一位线，以及将不同的第二电压提供给连接到第一选择晶体管的第二位线以被禁止编程; 接通多个单元串中的第二选择晶体管，并将第一编程电压提供给与第一选择晶体管连接的多个第一选择线中的所选择的第一选择线，以及将第三电压提供给未选择的第一选择线多个第一选择线。

4. 发明授权

US09136005B2 Erasing methods of three-dimensional nonvolatile memory devices with cell strings and dummy word lines 有权
标题翻译：具有单元串和虚拟字线的三维非易失性存储器件的擦除方法
公开(公告)号：US09136005B2
公开(公告)日：2015-09-15
申请号：US13784969
申请日：2013-03-05
申请人： Byeong-In Choe , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
发明人： Byeong-In Choe , Jaehoon Jang , Kihyun Kim , Sunil Shim , Woonkyung Lee
IPC分类号： G11C16/14 , G11C7/14 , G11C16/30 , H01L29/792 , H01L27/115 , G11C16/10 , G11C16/04 , G11C16/16
CPC分类号： G11C16/14 , G11C7/14 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/30 , H01L27/11582 , H01L29/7926
摘要： Methods of operating a nonvolatile memory device may include applying a word line erase voltage to word lines connected to memory cells of the plurality of cell strings, floating ground selection lines connected to ground selection transistors of the plurality of cell strings and string selection lines connected to string selection transistors of the plurality of cell strings, applying a ground voltage to at least one lower dummy word line connected to at least one lower dummy memory cell between memory cells and a ground selection transistor in each of the plurality of cell strings, applying an erase voltage to the substrate, and floating the at least one lower dummy word line after applying of the erase voltage.
摘要翻译：操作非易失性存储器件的方法可以包括将字线擦除电压施加到连接到多个单元串中的存储单元的字线，连接到多个单元串的接地选择晶体管的浮动地选择线和连接到多个单元串中的串选择晶体管，对连接到多个单元串中的每个单元串中的至少一个下存储单元之间的下虚拟存储单元的至少一个下虚拟字线施加接地电压，擦除电压到衬底，并且在施加擦除电压之后浮置至少一个下部虚拟字线。

5. 发明申请

US20120230103A1 Nonvolatile Memory Device And Operating Method Thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US20120230103A1
公开(公告)日：2012-09-13
申请号：US13289463
申请日：2011-11-04
申请人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
发明人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
IPC分类号： G11C16/06 , G11C16/04
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.
摘要翻译：根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。至少一个串可以包括含有多晶硅的通道。位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

6. 发明授权

US08724394B2 Nonvolatile memory device and operating method thereof 有权
标题翻译：非易失性存储器件及其操作方法
公开(公告)号：US08724394B2
公开(公告)日：2014-05-13
申请号：US13289463
申请日：2011-11-04
申请人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
发明人： Byeong-In Choe , Changseok Kang , Woonkyung Lee
IPC分类号： G11C11/34
CPC分类号： G11C16/0483 , G11C16/10 , H01L27/1157 , H01L27/11582 , H01L29/7926
摘要： According to example embodiments, a nonvolatile memory device includes a substrate, at least one string extending vertically from the substrate, and a bit line current controlling circuit connected to the at least one string via at least one bit line. The at least one string may include a channel containing polycrystalline silicon. The bit line current controlling circuit may be configured to increase the amount of current being supplied to the bit line according to a decrease in a temperature such that a current flowing through the channel of the at least one string is increased when a temperature decreases.
摘要翻译：根据示例性实施例，非易失性存储器件包括衬底，从衬底垂直延伸的至少一个串和经由至少一个位线连接到至少一个串的位线电流控制电路。至少一个串可以包括含有多晶硅的通道。位线电流控制电路可以被配置为根据温度的降低来增加提供给位线的电流量，使得当温度降低时流过至少一个串的通道的电流增加。

7. 发明授权

US08737129B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US08737129B2
公开(公告)日：2014-05-27
申请号：US13355834
申请日：2012-01-23
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/10 , G11C16/26 , G11C16/34 , G11C11/56
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

8. 发明授权

US09564237B2 Nonvolatile memory device and read method thereof 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US09564237B2
公开(公告)日：2017-02-07
申请号：US14946848
申请日：2015-11-20
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/04 , G11C16/26 , G11C16/30 , G11C8/10 , G11C11/56 , G11C16/10 , G11C16/34 , G11C29/00
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

9. 发明申请

US20120120732A1 NONVOLATILE MEMORY DEVICE AND READ METHOD THEREOF 有权
标题翻译：非易失性存储器件及其读取方法
公开(公告)号：US20120120732A1
公开(公告)日：2012-05-17
申请号：US13355834
申请日：2012-01-23
申请人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
发明人： Changhyun Lee , Jungdal Choi , Byeong-In Choe
IPC分类号： G11C16/10 , G11C16/26
CPC分类号： G11C16/26 , G11C8/10 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/10 , G11C16/3418 , G11C16/3436 , G11C16/3454 , G11C16/3459 , G11C29/00
摘要： A nonvolatile memory device has improved reliability by compensating a threshold voltage of a flash memory cell. A nonvolatile memory device includes a memory cell array and a voltage generator for supplying a select read voltage to a select word line and an unselect read voltage to unselected word lines when a read operation is performed, and supplying a verify voltage to a select word line and the unselect read voltage to unselected word lines when a program operation is performed. The voltage generator supplies a first unselect read voltage to at least one between an upper word line and a lower word line adjacent to the select word line when the program operation is performed, and supplies a second unselected read voltage to at least one between the upper word line and the lower word line adjacent to the select word line when the read operation is performed.
摘要翻译：非易失性存储器件通过补偿闪存单元的阈值电压而提高了可靠性。非易失性存储器件包括：存储单元阵列和电压发生器，用于在执行读取操作时将选择读取电压提供给选择字线，并将未选择读取电压提供给未选择的字线;以及将验证电压提供给选择字线以及当执行编程操作时，对未选字线的取消选择读取电压。电压发生器在执行编程操作时将第一未读选择电压提供给与选择字线相邻的上字线和下字线之间的至少一个，并且将第二未选择读电压提供给上当执行读操作时，字线和与选择字线相邻的下字线。

10. 发明申请

US20120003828A1 SEMICONDUCTOR MEMORY DEVICE AND METHOD OF FORMING THE SAME 审中-公开
标题翻译：半导体存储器件及其形成方法
公开(公告)号：US20120003828A1
公开(公告)日：2012-01-05
申请号：US13173321
申请日：2011-06-30
申请人： Sung-Il Chang , Changseok Kang , Byeong-In Choe
发明人： Sung-Il Chang , Changseok Kang , Byeong-In Choe
IPC分类号： H01L21/28
CPC分类号： H01L27/11582 , H01L27/1157 , H01L29/4234 , H01L29/792
摘要： A method of manufacturing a semiconductor device includes forming a laminated structure including sacrificial layers and a select gate layer on a substrate, forming a penetration region penetrating the laminated structure, forming a select gate insulating layer on a sidewall of the select gate layer exposed by the penetration region, and forming an active pattern in the penetration region. The method also includes exposing a portion of the active pattern by removing the sacrificial layers and forming an information storage layer on the exposed portion of the active pattern.
摘要翻译：一种制造半导体器件的方法包括在衬底上形成包括牺牲层和选择栅极层的叠层结构，形成穿透层叠结构的穿透区域，在选择栅极层的侧壁上形成选择栅极绝缘层，穿透区域，并且在穿透区域中形成活性图案。该方法还包括通过去除牺牲层并在活性图案的暴露部分上形成信息存储层来暴露活性图案的一部分。

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