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1. 发明申请

US20080157200A1 STRESS LINER SURROUNDED FACETLESS EMBEDDED STRESSOR MOSFET 审中-公开
标题翻译：应力衬里无缝嵌入式应力MOSFET
公开(公告)号：US20080157200A1
公开(公告)日：2008-07-03
申请号：US11616730
申请日：2006-12-27
申请人： Byeong Y. Kim , Shahid A. Butt , Xiaomeng Chen , Shwu-Jen J. Jeng , Hasan M. Nayfeh , Deepal Wehella-Gamage
发明人： Byeong Y. Kim , Shahid A. Butt , Xiaomeng Chen , Shwu-Jen J. Jeng , Hasan M. Nayfeh , Deepal Wehella-Gamage
IPC分类号： H01L29/78
CPC分类号： H01L29/66636 , H01L29/165 , H01L29/201 , H01L29/221 , H01L29/66628 , H01L29/66772 , H01L29/78 , H01L29/7846 , H01L29/7848 , H01L29/78684
摘要： The present invention provides an STI bounded transistor structure having enhanced performance which is not diminished due to embedded stressor facets that can be present at the edge of the source/drain regions that contacts an embedded stressor material. Considering that the facet in the prior art is due to an STI divot formed during several necessary wet etching processes, the MOSFET source/drain edge of the inventive structure is surrounded by a liner to prevent facet growth during the epitaxial growth of the stressor material. As such, a part of the semiconductor substrate edge is preserved. The liner employed in the present invention is a stress engineering material such as, for example, silicon nitride.
摘要翻译：本发明提供了一种具有增强性能的STI界限晶体管结构，其由于可能存在于接触嵌入的应力源材料的源极/漏极区域的边缘处的嵌入的应力小面而不会减小。考虑到现有技术中的方面是由于在几个必要的湿蚀刻工艺期间形成的STI纹路，本发明结构的MOSFET源极/漏极边缘被衬垫围绕，以防止在应力源材料的外延生长期间的面生长。因此，半导体衬底边缘的一部分被保留。本发明中使用的衬垫是应力工程材料，例如氮化硅。

2. 发明授权

US08754446B2 Semiconductor structure having undercut-gate-oxide gate stack enclosed by protective barrier material 有权
标题翻译：半导体结构具有由保护性阻挡材料包围的底切栅氧化物栅叠层
公开(公告)号：US08754446B2
公开(公告)日：2014-06-17
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

3. 发明授权

US07491623B2 Method of making a semiconductor structure 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US07491623B2
公开(公告)日：2009-02-17
申请号：US11841018
申请日：2007-08-20
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L21/76
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

4. 发明申请

US20080121931A1 SEMICONDUCTOR STRUCTURE AND METHOD OF MAKING SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20080121931A1
公开(公告)日：2008-05-29
申请号：US11468403
申请日：2006-08-30
申请人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
发明人： Xiaomeng Chen , Shwu-Jen Jeng , Byeong Y. Kim , Hasan M. Nayfeh
IPC分类号： H01L29/772
CPC分类号： H01L29/7848 , H01L21/823814 , H01L29/165 , H01L29/6653 , H01L29/66628 , H01L29/66636 , H01L29/78
摘要： The invention is directed to a structure and method of forming a structure having a sealed gate oxide layer. The structure includes a gate oxide layer formed on a substrate and a gate formed on the gate oxide layer. The structure further includes a material abutting walls of the gate and formed within an undercut underneath the gate to protect regions of the gate oxide layer exposed by the undercut. Source and drain regions are isolated from the gate by the material.
摘要翻译：本发明涉及形成具有密封栅极氧化物层的结构的结构和方法。该结构包括在衬底上形成的栅极氧化层和形成在栅极氧化物层上的栅极。该结构还包括栅极的材料邻接壁并形成在栅极下方的底切之下，以保护由底切露出的栅极氧化物层的区域。源极和漏极区域通过材料与栅极隔离。

5. 发明授权

US08017483B2 Method of creating asymmetric field-effect-transistors 有权
标题翻译：制造不对称场效应晶体管的方法
公开(公告)号：US08017483B2
公开(公告)日：2011-09-13
申请号：US12493549
申请日：2009-06-29
申请人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
发明人： Gregory G. Freeman , Shreesh Narasimha , Ning Su , Hasan M. Nayfeh , Nivo Rovedo , Werner A. Rausch , Jian Yu
IPC分类号： H01L21/336
CPC分类号： H01L21/823425 , H01L21/26586 , H01L21/823412 , H01L29/66492 , H01L29/66659
摘要： The present invention provides a method of forming asymmetric field-effect-transistors. The method includes forming at least a first and a second gate-mask stack on top of a semiconductor substrate, wherein the first and second gate-mask stacks include at least, respectively, a first and a second gate conductor of a first and a second transistor and have, respectively, a top surface, a first side, and a second side with the second side being opposite to the first side; performing a first halo implantation from the first side of the first and second gate-mask stacks at a first angle while applying the first gate-mask stack in preventing the first halo implantation from reaching a first source/drain region of the second transistor, wherein the first angle is equal to or larger than a predetermined value; and performing a second halo implantation from the second side of the first and second gate-mask stacks at a second angle, thereby creating halo implant in a second source/drain region of the second transistor, wherein the first and second angles are measured against a normal to the substrate.
摘要翻译：本发明提供了形成非对称场效应晶体管的方法。该方法包括在半导体衬底的顶部上形成至少第一和第二栅极掩模叠层，其中第一和第二栅极掩模叠层至少分别包括第一和第二栅极掩模叠层的第一和第二栅极导体分别具有顶表面，第一侧和第二侧，第二侧与第一侧相对; 以第一角度从第一和第二栅极掩模叠层的第一侧进行第一光晕注入，同时施加第一栅极掩模叠层以防止第一光晕注入到达第二晶体管的第一源极/漏极区域，其中第一角度等于或大于预定值; 以及以第二角度从所述第一和第二栅极掩模叠层的第二侧执行第二光晕注入，从而在所述第二晶体管的第二源极/漏极区域中产生晕轮注入，其中所述第一和第二角度是针对与基底垂直。

6. 发明申请

US20110089499A1 STRUCTURE AND METHOD FOR MANUFACTURING ASYMMETRIC DEVICES 有权
公开(公告)号：US20110089499A1
公开(公告)日：2011-04-21
申请号：US12581924
申请日：2009-10-20
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L29/78 , H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.

7. 发明申请

US20120217585A1 Structure and Method for Manufacturing Asymmetric Devices 有权
标题翻译：制造不对称设备的结构和方法
公开(公告)号：US20120217585A1
公开(公告)日：2012-08-30
申请号：US13468270
申请日：2012-05-10
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L27/088
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

8. 发明授权

US08232151B2 Structure and method for manufacturing asymmetric devices 有权
标题翻译：用于制造不对称装置的结构和方法
公开(公告)号：US08232151B2
公开(公告)日：2012-07-31
申请号：US13167303
申请日：2011-06-23
申请人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
发明人： Hasan M. Nayfeh , Andres Bryant , Arvind Kumar , Nivo Rovedo , Robert R. Robison
IPC分类号： H01L21/336
CPC分类号： H01L21/26586 , H01L29/1083 , H01L29/66492 , H01L29/66545 , H01L29/66659
摘要： A plurality of gate structures are formed on a substrate. Each of the gate structures includes a first gate electrode and source and drain regions. The first gate electrode is removed from each of the gate structures. A first photoresist is applied to block gate structures having source regions in a source-down direction. A first halo implantation is performed in gate structures having source regions in a source-up direction at a first angle. The first photoresist is removed. A second photoresist is applied to block gate structures having source regions in a source-up direction. A second halo implantation is performed in gate structures having source regions in a source-down direction at a second angle. The second photoresist is removed. Replacement gate electrodes are formed in each of the gate structures.
摘要翻译：在基板上形成多个栅极结构。每个栅极结构包括第一栅极电极和源极和漏极区域。从每个栅极结构去除第一栅电极。施加第一光致抗蚀剂以在源向下方向上阻挡具有源极区的栅极结构。在栅极结构中进行第一光晕注入，其栅源结构的源极区域在源极方向上以第一角度。去除第一光致抗蚀剂。施加第二光致抗蚀剂以阻挡在源向上方向上具有源极区的栅极结构。在栅极结构中进行第二光晕注入，其栅源结构的源极区域以源向下方向为第二角度。去除第二光致抗蚀剂。在每个栅极结构中形成替代栅电极。

9. 发明授权

US07151023B1 Metal gate MOSFET by full semiconductor metal alloy conversion 失效
标题翻译：金属栅极MOSFET采用全半导体金属合金转换
公开(公告)号：US07151023B1
公开(公告)日：2006-12-19
申请号：US11161372
申请日：2005-08-01
申请人： Hasan M. Nayfeh , Mahender Kumar , Sunfei Fang , Jakub T Kedzierski , Cyril Cabral, Jr.
发明人： Hasan M. Nayfeh , Mahender Kumar , Sunfei Fang , Jakub T Kedzierski , Cyril Cabral, Jr.
IPC分类号： H01L21/8238 , H01L21/336 , H01L21/8234 , H01L21/4763 , H01L29/00
CPC分类号： H01L21/823835 , H01L21/823842 , H01L29/66545 , H01L29/6659 , H01L29/7833
摘要： A MOSFET structure and method of forming is described. The method includes forming a metal-containing layer that is thick enough to fully convert the semiconductor gate stack to a semiconductor metal alloy in a first MOSFET type region but only thick enough to partially convert the semiconductor gate stack to a semiconductor metal alloy in a second MOSFET type region. In one embodiment, the gate stack in a first MOSFET region is recessed prior to forming the metal-containing layer so that the height of the first MOSFET semiconductor stack is less than the height of the second MOSFET semiconductor stack. In another embodiment, the metal-containing layer is thinned over one MOSFET region relative to the other MOSFET region prior to the conversion process.
摘要翻译：描述了MOSFET结构和形成方法。该方法包括形成足够厚的含金属层，以将半导体栅极堆叠完全转换成第一MOSFET型区域中的半导体金属合金，但是仅仅足够厚以将第二半导体栅极堆叠部分地转换成半导体金属合金 MOSFET类型区域。在一个实施例中，在形成含金属层之前，第一MOSFET区域中的栅极堆叠是凹进的，使得第一MOSFET半导体堆叠的高度小于第二MOSFET半导体堆叠的高度。在另一个实施例中，在转换过程之前，含金属层相对于另一个MOSFET区域在一个MOSFET区域上变薄。

10. 发明申请

US20130015580A1 REPLACEMENT METAL GATE STRUCTURE AND METHODS OF MANUFACTURE 有权
标题翻译：替代金属门结构和制造方法
公开(公告)号：US20130015580A1
公开(公告)日：2013-01-17
申请号：US13180842
申请日：2011-07-12
申请人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
发明人： SAMEER H JAIN , Jeffrey B. Johnson , Ying Li , Hasan M. Nayfeh , Ravikumar Ramachandran
IPC分类号： H01L29/423 , H01L21/28
CPC分类号： H01L29/66545 , H01L21/28088 , H01L21/28167 , H01L21/823807 , H01L21/823842 , H01L21/823857 , H01L21/823864 , H01L29/165 , H01L29/4966 , H01L29/513 , H01L29/517 , H01L29/665 , H01L29/6659 , H01L29/66636 , H01L29/7843
摘要： A replacement metal gate structure and methods of manufacturing the same is provided. The method includes forming at least one trench structure and forming a liner of high-k dielectric material in the at least one trench structure. The method further includes adjusting a height of the liner of high-k dielectric material. The method further includes forming at least one workfunction metal over the liner, and forming a metal gate structure in the at least one trench structure, over the at least one workfunction metal and the liner of high-k dielectric material.
摘要翻译：提供替代的金属栅极结构及其制造方法。所述方法包括形成至少一个沟槽结构并在所述至少一个沟槽结构中形成高k电介质材料的衬垫。该方法还包括调整高k电介质材料的衬垫的高度。所述方法还包括在所述衬垫上形成至少一个功函数金属，以及在所述至少一个功函数金属和所述高k电介质材料的衬垫上，在所述至少一个沟槽结构中形成金属栅极结构。

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