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1. 发明申请

US20140264516A1 METHODS OF FORMING PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 有权
标题翻译：形成图案的方法和使用该方法制造半导体器件的方法
公开(公告)号：US20140264516A1
公开(公告)日：2014-09-18
申请号：US14210329
申请日：2014-03-13
申请人： Bum-Seok SEO , Ki-Joon KIM , Kil-Ho LEE
发明人： Bum-Seok SEO , Ki-Joon KIM , Kil-Ho LEE
IPC分类号： H01L43/02 , H01L43/12
CPC分类号： H01L27/228 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/82 , H01L43/02 , H01L43/08 , H01L43/12
摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
摘要翻译：在基板上形成绝缘层。在绝缘层上形成第一掩模。第一掩模包括沿第二方向布置的多个线图案。多个线图案沿着基本上垂直于第二方向的第一方向延伸。在绝缘层和第一掩模上形成第二掩模。第二掩模包括部分地暴露多个线图案的开口。开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。多个第一沟槽和第二沟槽以交错图案布置。

2. 发明申请

US20150325625A1 METHODS OF FORMING PATTERNS AND METHODS OF MANUFACTURING SEMICONDUCTOR DEVICES USING THE SAME 有权
标题翻译：形成图案的方法和使用该方法制造半导体器件的方法
公开(公告)号：US20150325625A1
公开(公告)日：2015-11-12
申请号：US14804310
申请日：2015-07-20
申请人： Bum-Seok SEO , Ki-Joon KIM , Kil-Ho LEE
发明人： Bum-Seok SEO , Ki-Joon KIM , Kil-Ho LEE
IPC分类号： H01L27/22 , H01L43/08 , H01L43/02
CPC分类号： H01L27/228 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L29/82 , H01L43/02 , H01L43/08 , H01L43/12
摘要： An insulation layer is formed on a substrate. A first mask is formed on the insulation layer. The first mask includes a plurality of line patterns arranged in a second direction. The plurality of line patterns extend in a first direction substantially perpendicular to the second direction. A second mask is formed on the insulation layer and the first mask. The second mask includes an opening partially exposing the plurality of line patterns. The opening has an uneven boundary at one of a first end portion in the first direction and a second end portion in a third direction substantially opposite to the first direction. The insulation layer is partially removed using the first mask and the second mask as an etching mask, thereby forming a plurality of first trenches and second trenches. The plurality of first trenches and the second trenches are arranged in a staggered pattern.
摘要翻译：在基板上形成绝缘层。在绝缘层上形成第一掩模。第一掩模包括沿第二方向布置的多个线图案。多个线图案沿着基本上垂直于第二方向的第一方向延伸。在绝缘层和第一掩模上形成第二掩模。第二掩模包括部分地暴露多个线图案的开口。开口在第一方向的第一端部和第一方向的第三方向的第二方向的第一方向的一侧具有不均匀的边界。使用第一掩模和第二掩模作为蚀刻掩模来部分去除绝缘层，从而形成多个第一沟槽和第二沟槽。多个第一沟槽和第二沟槽以交错图案布置。

3. 发明申请

US20140038385A1 NONVOLATILE MEMORY DEVICES AND METHODS OF FABRICATING THE SAME 有权
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US20140038385A1
公开(公告)日：2014-02-06
申请号：US13946307
申请日：2013-07-19
申请人： Kil-Ho LEE , Ki-Joon KIM , Se-Woong PARK
发明人： Kil-Ho LEE , Ki-Joon KIM , Se-Woong PARK
IPC分类号： H01L21/762
CPC分类号： H01L21/76224 , H01L21/76805 , H01L21/76808 , H01L21/76831 , H01L21/76832 , H01L27/228 , H01L43/08
摘要： Nonvolatile memory devices and methods of fabricating the same, include, forming a transistor in a first region of a substrate, forming a contact which is connected to the transistor, forming an information storage portion, which is disposed two-dimensionally, in a second region of the substrate, sequentially forming a stop film and an interlayer insulating film which cover the contact and the information storage portion, forming a first trench, which exposes the stop film, on the contact, and forming a second trench which extends through the stop film to expose the contact, wherein a bottom surface of the first trench is lower than a bottom surface of the information storage portion.
摘要翻译：非易失性存储器件及其制造方法包括：在衬底的第一区域中形成晶体管，形成连接到晶体管的触点，形成二维地设置在第二区域中的信息存储部分的基板，顺序地形成覆盖接触的信息存储部分的停止膜和层间绝缘膜，形成在接触件上露出停止膜的第一沟槽，并形成延伸穿过停止膜的第二沟槽暴露触点，其中第一沟槽的底表面低于信息存储部分的底面。

4. 发明申请

US20140377950A1 METHOD OF MANUFACTURING A SEMICONDUCTOR DEVICE 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US20140377950A1
公开(公告)日：2014-12-25
申请号：US14285969
申请日：2014-05-23
申请人： Yong-Jun KIM , Kil-Ho LEE , Ki-Joon KIM , Myoung-Su SON
发明人： Yong-Jun KIM , Kil-Ho LEE , Ki-Joon KIM , Myoung-Su SON
IPC分类号： H01L21/768
CPC分类号： H01L21/76807
摘要： A method of manufacturing a semiconductor device, including forming a molding layer; forming a damascene mask layer and mask layer on the molding layer; forming a mask layer pattern by etching the mask layer; forming a damascene pattern by partially etching the damascene mask layer; forming a damascene mask layer on the mask layer pattern to bury the damascene pattern; forming a damascene pattern partially overlapping the damascene pattern by etching the damascene mask layer and the mask layer pattern; connecting the damascene pattern and the damascene pattern by removing a portion of the mask layer pattern exposed by the damascene pattern; forming a damascene mask layer on the damascene mask layer to bury the damascene pattern; and forming a trench under the damascene patterns by etching the damascene mask layers and the molding layer using remaining portions of the mask layer pattern.
摘要翻译：一种制造半导体器件的方法，包括形成模制层; 在成型层上形成镶嵌掩模层和掩模层; 通过蚀刻掩模层形成掩模层图案; 通过部分蚀刻镶嵌掩模层形成镶嵌图案; 在掩模层图案上形成镶嵌掩模层以埋藏镶嵌图案; 通过蚀刻镶嵌掩模层和掩模层图案形成部分地与镶嵌图案重叠的镶嵌图案; 通过去除由镶嵌图案暴露的掩模层图案的一部分来连接镶嵌图案和镶嵌图案; 在镶嵌掩模层上形成镶嵌掩模层，以埋藏镶嵌图案; 以及通过使用掩模层图案的剩余部分蚀刻镶嵌掩模层和模制层，在镶嵌图案之下形成沟槽。

5. 发明申请

US20170069684A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20170069684A1
公开(公告)日：2017-03-09
申请号：US15157403
申请日：2016-05-17
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
IPC分类号： H01L27/22 , H01L43/02 , H01L43/10 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.
摘要翻译：制造MRAM器件的方法包括在衬底上依次形成第一绝缘层和蚀刻停止层。通过蚀刻停止层和第一绝缘中间层形成下电极。在下电极和蚀刻停止层上依次形成MTJ结构层和上电极。通过使用上电极作为蚀刻掩模的物理蚀刻工艺对MTJ结构层进行构图，以形成至少部分地接触下电极的MTJ结构。第一绝缘中间层由蚀刻停止层保护，因此不被物理蚀刻工艺蚀刻。

6. 发明申请

US20180012933A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICE AND METHOD OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20180012933A1
公开(公告)日：2018-01-11
申请号：US15712130
申请日：2017-09-21
申请人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
发明人： Ki-Seok SUH , Jae-Chul SHIM , Kil-Ho LEE , Yong-Seok CHUNG , Gwan-Hyeob KOH , Yoon-Jong SONG
IPC分类号： H01L27/22 , H01L43/12
CPC分类号： H01L27/222 , H01L43/12
摘要： A method of manufacturing an MRAM device includes sequentially forming a first insulating interlayer and an etch-stop layer on a substrate. A lower electrode is formed through the etch-stop layer and the first insulating interlayer. An MTJ structure layer and an upper electrode are sequentially formed on the lower electrode and the etch-stop layer. The MTJ structure layer is patterned by a physical etching process using the upper electrode as an etching mask to form an MTJ structure at least partially contacting the lower electrode. The first insulating interlayer is protected by the etch-stop layer so not to be etched by the physical etching process.

7. 发明申请

US20150188037A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20150188037A1
公开(公告)日：2015-07-02
申请号：US14453110
申请日：2014-08-06
申请人： Kyung-Tae NAM , Kil-Ho LEE
发明人： Kyung-Tae NAM , Kil-Ho LEE
IPC分类号： H01L43/12 , H01L43/08 , H01L27/22 , H01L43/02
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.
摘要翻译：在制造MRAM器件的方法中，可以形成顺序堆叠在衬底上的下电极，第一钉扎层图案，隧道势垒层图案和自由层图案。可以在基板上形成第一绝缘中间层以覆盖下电极，第一钉扎层图案，隧道势垒层图案和自由层图案。可以蚀刻第一绝缘中间层以形成露出自由层图案的顶表面的凹部。可以形成第二钉扎层图案以填充凹部的至少一部分。可以在第二钉扎层图案上形成布线。

8. 发明申请

US20160276575A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 审中-公开
公开(公告)号：US20160276575A1
公开(公告)日：2016-09-22
申请号：US15170409
申请日：2016-06-01
申请人： Kyung-Tae NAM , Kil-Ho LEE
发明人： Kyung-Tae NAM , Kil-Ho LEE
IPC分类号： H01L43/02 , H01L27/22 , H01L43/12 , H01L43/08 , H01L43/10
CPC分类号： H01L43/02 , G11C11/161 , H01L27/228 , H01L43/08 , H01L43/10 , H01L43/12
摘要： In a method of manufacturing an MRAM device, a lower electrode, a first pinning layer pattern, a tunnel barrier layer pattern and a free layer pattern sequentially stacked on a substrate may be formed. A first insulating interlayer may be formed on the substrate to cover the lower electrode, the first pinning layer pattern, the tunnel barrier layer pattern and the free layer pattern. The first insulating interlayer may be etched to form a recess exposing a top surface of the free layer pattern. A second pinning layer pattern may be formed to fill at least a portion of the recess. A wiring may be formed on the second pinning layer pattern.

9. 发明申请

US20160020249A1 MAGNETORESISTIVE RANDOM ACCESS MEMORY DEVICES AND METHODS OF MANUFACTURING THE SAME 有权
标题翻译：磁性随机访问存储器件及其制造方法
公开(公告)号：US20160020249A1
公开(公告)日：2016-01-21
申请号：US14804321
申请日：2015-07-20
申请人： Seung-Pil KO , Myoung-Su SON , Kil-Ho LEE
发明人： Seung-Pil KO , Myoung-Su SON , Kil-Ho LEE
IPC分类号： H01L27/22 , H01L43/02 , H01L43/12 , H01L43/08
CPC分类号： H01L27/222 , H01L27/228 , H01L43/02 , H01L43/08 , H01L43/12
摘要： An MRAM device comprises an insulating interlayer comprising a flat first upper surface on a first region and a second region of a substrate. A pattern structure comprising pillar-shaped magnetic tunnel junction (MTJ) structures and a filling layer pattern between the MTJ structures is formed on the insulating interlayer of the first region. The pattern structure comprises a flat second upper surface that is higher than the first upper surface. Bit lines are formed on the pattern structure that contact top surfaces of the MTJ structures. An etch-stop layer is formed on the pattern structure between the bit lines of the first region and the first upper surface of the first insulating interlayer of the second region. A first portion of an upper surface of the etch-stop layer on the first region is higher than a second portion of the upper surface of the etch-stop layer on the second region.
摘要翻译： MRAM器件包括绝缘中间层，其包括在第一区域上的平坦的第一上表面和衬底的第二区域。在第一区域的绝缘中间层上形成包括柱形磁隧道结（MTJ）结构和MTJ结构之间的填充层图案的图案结构。图案结构包括比第一上表面高的扁平的第二上表面。位线形成在与MTJ结构的顶表面接触的图案结构上。在第一区域的位线和第二区域的第一绝缘中间层的第一上表面之间的图案结构上形成蚀刻停止层。第一区域上的蚀刻停止层的上表面的第一部分高于第二区域上的蚀刻停止层的上表面的第二部分。

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