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1. 发明授权

US07465621B1 Method of fabricating a switching regulator with a high-side p-type device 有权
标题翻译：制造具有高侧p型器件的开关调节器的方法
公开(公告)号：US07465621B1
公开(公告)日：2008-12-16
申请号：US11232516
申请日：2005-09-21
申请人： Budong You , Marco A. Zuniga , Andrew J. Burstein
发明人： Budong You , Marco A. Zuniga , Andrew J. Burstein
IPC分类号： H01L21/8238
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823857 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/66681 , H01L29/7835
摘要： A first impurity region of a first type is implanted to have a first surface area on a substrate. A second impurity region of an opposite second type is implanted into a drain region of the transistor to have a second surface area in the first surface area of the first impurity region. A gate oxide is formed after implantation of the second impurity region between a source region and the drain region of the transistor, and the gate oxide is covered with a conductive material. A third impurity region of the opposite second type and a fourth impurity region of the first type are implanted into the source region of the transistor in the first surface area. A fifth impurity region of the opposite second type is implanted into the drain region of the transistor in the second surface area of the second impurity region.
摘要翻译：植入第一类型的第一杂质区域以在衬底上具有第一表面区域。相反的第二类型的第二杂质区被注入晶体管的漏极区，以在第一杂质区的第一表面区域具有第二表面积。在晶体管的源极区域和漏极区域上注入第二杂质区域之后形成栅极氧化物，并且栅极氧化物被导电材料覆盖。第一类型的第三杂质区和第一类型的第四杂质区注入到第一表面区中的晶体管的源极区中。相反的第二类型的第五杂质区域注入第二杂质区域的第二表面区域中的晶体管的漏极区域。

2. 发明授权

US07038274B2 Switching regulator with high-side p-type device 有权
标题翻译：具有高侧p型器件的开关稳压器
公开(公告)号：US07038274B2
公开(公告)日：2006-05-02
申请号：US10714141
申请日：2003-11-13
申请人： Budong You , Marco A. Zuniga , Andrew J. Burstein
发明人： Budong You , Marco A. Zuniga , Andrew J. Burstein
IPC分类号： H01L31/062 , H01L29/76 , H01L29/94 , H01L31/113 , H01L31/119
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823857 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0878 , H01L29/42368 , H01L29/66681 , H01L29/7835
摘要： A voltage regulator having an input terminal and an output terminal. A PMOS transistor connects the input terminal to an intermediate terminal. The PMOS transistor includes a first gate oxide layer. An LDMOS transistor connects the intermediate terminal to ground. The LDMOS transistor includes a second gate oxide layer. A controller drives the PMOS transistor and the LDMOS transistor to alternately couple the intermediate terminal between the input terminal and ground, to generate an intermediate voltage at the intermediate terminal having a rectangular waveform. A filter is disposed between the intermediate terminal and the output terminal to convert the rectangular waveform into a substantially DC voltage at the output terminal.
摘要翻译：具有输入端子和输出端子的电压调节器。 PMOS晶体管将输入端子连接到中间端子。 PMOS晶体管包括第一栅极氧化物层。 LDMOS晶体管将中间端子连接到地。 LDMOS晶体管包括第二栅极氧化物层。控制器驱动PMOS晶体管和LDMOS晶体管，以在输入端和地之间交替耦合中间端子，以在具有矩形波形的中间端产生中间电压。滤波器设置在中间端子和输出端子之间，以将矩形波形转换成输出端子上的大致直流电压。

3. 发明授权

US07981739B1 Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor 有权
标题翻译：制造横向双扩散MOSFET（LDMOS）晶体管和常规CMOS晶体管的方法
公开(公告)号：US07981739B1
公开(公告)日：2011-07-19
申请号：US12710154
申请日：2010-02-22
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H01L21/8238
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823857 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/66674 , H01L29/7801 , H01L29/7824
摘要： A method of fabricating an LDMOS transistor and a conventional CMOS transistor together on a substrate. A P-body is implanted into a source region of the LDMOS transistor. A gate oxide for the conventional CMOS transistor is formed after implanting the P-body into the source region of the LDMOS transistor. A fixed thermal cycle associated with forming the gate oxide of the conventional CMOS transistor is not substantially affected by the implanting of the P-body into the source region of the LDMOS transistor.
摘要翻译：一种在衬底上一起制造LDMOS晶体管和常规CMOS晶体管的方法。 P体被注入到LDMOS晶体管的源极区域中。在将P体注入到LDMOS晶体管的源极区域之后，形成用于传统CMOS晶体管的栅极氧化物。与形成常规CMOS晶体管的栅极氧化物相关联的固定热循环基本上不受P体注入LDMOS晶体管的源极区域的影响。

4. 发明授权

US06703888B1 Method of operating circuit with FET transistor pair 有权
标题翻译： FET晶体管对工作电路的方法
公开(公告)号：US06703888B1
公开(公告)日：2004-03-09
申请号：US10327586
申请日：2002-12-20
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H03K17687
CPC分类号： H03K5/15 , H03K5/08 , H03K17/167 , H03K17/302
摘要： A method for use with a switch having a field-effect transistor (FET). The method includes restricting the drain-source voltage of the FET to a predetermined range, and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal, a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal, and a control circuit coupled to the gate terminal, the first gate, and the second gate.
摘要翻译：一种与具有场效应晶体管（FET）的开关一起使用的方法。该方法包括将FET的漏 - 源电压限制在预定范围内，然后切换FET。通常，一方面，本发明的特征在于具有源极，漏极和栅极端子的电路。电路包括具有耦合到漏极端子的第一漏极和耦合到源极端子的第一源极的第一FET，具有耦合到漏极端子的第二漏极和耦合到源极端子的第二源极的第二FET，以及控制器电路耦合到栅极端子，第一栅极和第二栅极。

5. 发明授权

US08405148B1 Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor and a conventional CMOS transistor 有权
公开(公告)号：US08405148B1
公开(公告)日：2013-03-26
申请号：US13185356
申请日：2011-07-18
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H01L29/66
CPC分类号： H01L29/7816 , H01L21/823814 , H01L21/823857 , H01L21/8249 , H01L27/0623 , H01L27/0922 , H01L29/0847 , H01L29/086 , H01L29/0878 , H01L29/66674 , H01L29/7801 , H01L29/7824
摘要： An integrated circuit structure having an LDMOS transistor and a CMOS transistor includes a p-type substrate having a surface, an n-well implanted in the substrate, the first n-well providing a CMOS n-well, a CMOS transistor including a CMOS source with a first p+ region implanted in the n-well, a CMOS drain with a second p+ region implanted in the n-well, and a CMOS gate between the first p+ region and the second p+ region, and an LDMOS transistor including an LDMOS source with an LDMOS source including a p-body implanted in the n-well, a third p+ region implanted in the p-body, and a first n+ region implanted in the p-body, an LDMOS drain including an n-doped shallow drain implanted in the n-well, and a second n+ region implanted in the n-doped shallow drain, and an LDMOS gate between the third p+ region and the second n+ region.

6. 发明申请

US20110269286A1 HEAVILY DOPED REGION IN DOUBLE-DIFFUSED SOURCE MOSFET (LDMOS) TRANSISTOR AND A METHOD OF FABRICATING THE SAME 有权
标题翻译：双通道MOSFET（LDMOS）晶体管中的重掺杂区域及其制造方法
公开(公告)号：US20110269286A1
公开(公告)日：2011-11-03
申请号：US13184333
申请日：2011-07-15
申请人： Marco A. Zuniga , Budong You
发明人： Marco A. Zuniga , Budong You
IPC分类号： H01L21/336
CPC分类号： H01L21/041 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/66689 , H01L29/7816 , H01L29/7836
摘要： A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.
摘要翻译：晶体管包括源极，漏极和栅极。源包括p掺杂的p体，与p体重叠的p +区，与p +区相邻的p体重叠的n +区，以及n掺杂源，重双扩散（SHDD）区仅在晶体管的源极区域中，SHDD区域的深度大约等于第一n +区域的深度并且与第一n +区域重叠。漏极包括与第二n +区重叠的第二n +区和n掺杂的浅漏极。栅极包括栅极氧化物和栅极氧化物上的导电材料。 SHDD区域比栅极氧化物下面的第一n +区域进一步横向延伸。使用大于n掺杂浅漏极的掺杂浓度的掺杂浓度注入SHDD区，但是小于第一n +区的杂质浓度。

7. 发明授权

US07405117B2 Method of fabricating a lateral double-diffused MOSFET (LDMOS) transistor 有权
标题翻译：制造横向双扩散MOSFET（LDMOS）晶体管的方法
公开(公告)号：US07405117B2
公开(公告)日：2008-07-29
申请号：US11435079
申请日：2006-05-15
申请人： Marco A. Zuniga , Budong You
发明人： Marco A. Zuniga , Budong You
IPC分类号： H01L21/336
CPC分类号： H01L29/7816 , H01L21/823807 , H01L21/823814 , H01L21/823892 , H01L29/0696 , H01L29/086 , H01L29/0878 , H01L29/1095 , H01L29/66681 , H01L29/66689 , H01L29/7835
摘要： A method of monolithically fabricating a lateral double-diffused MOSFET (LDMOS) transistor having a source, drain, and a gate on a substrate, with a process flow that is compatible with a CMOS process flow, is disclosed.
摘要翻译：公开了一种采用与CMOS工艺流程兼容的工艺流程来单片地制造在衬底上具有源极，漏极和栅极的横向双扩散MOSFET（LDMOS）晶体管的方法。

8. 发明授权

US07230470B1 Power switch using a field-effect transistor (FET) pair 有权
标题翻译：使用场效应晶体管（FET）对的电源开关
公开(公告)号：US07230470B1
公开(公告)日：2007-06-12
申请号：US11215589
申请日：2005-08-29
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H03K17/687
CPC分类号： H03K17/167 , H03K17/082 , H03K17/6871
摘要： A power switch, and a method, for use with a power switch having a field-effect transistor (FET) including source, drain and gate terminals. The power switch includes a first field-effect transistor (FET) having a first drain coupled to the drain terminal, a first source coupled to the source terminal, and a first gate; and, a second FET having a second drain coupled to the drain terminal, a second source coupled to the source terminal, and a second gate. The second FET has a gate length (LG) that is greater than or less than an LG of the first FET and has a length of a drain (LD) that is greater than or less than an LD of the first FET. The power switch further includes a control circuit coupled to the gate terminal, the first gate, and the second gate.
摘要翻译：一种用于具有包括源极，漏极和栅极端子的场效应晶体管（FET）的功率开关的电源开关和方法。电源开关包括：具有耦合到漏极端子的第一漏极的第一场效应晶体管（FET），耦合到源极端子的第一源极和第一栅极; 以及具有耦合到所述漏极端子的第二漏极的第二FET，耦合到所述源极端子的第二源极和第二栅极。第二FET具有大于或小于第一FET的L SC的栅极长度（L SUB），并且具有漏极的长度（L _{D>大于或小于第一FET的L D D的大小。电源开关还包括耦合到栅极端子，第一栅极和第二栅极的控制电路。}

9. 发明授权

US06529056B1 Circuit with FET transistor pair 有权
标题翻译：电路与FET晶体管对
公开(公告)号：US06529056B1
公开(公告)日：2003-03-04
申请号：US10172484
申请日：2002-06-13
申请人： Budong You , Marco A. Zuniga
发明人： Budong You , Marco A. Zuniga
IPC分类号： H03K17687
CPC分类号： H03K17/167 , H03K5/08 , H03K5/15 , H03K17/302
摘要： A circuit, and a method and computer program product for use with a switch having a field-effect transistor (FET). The method and computer program product include restricting the drain-source voltage of the FET to a predetermined range; and then switching the FET. In general, in one aspect, the invention features a circuit having source, drain and gate terminals. The circuit includes a first FET having a first drain coupled to the drain terminal and a first source coupled to the source terminal; a second FET having a second drain coupled to the drain terminal and a second source coupled to the source terminal; and a control circuit coupled to the gate terminal, the first gate, and the second gate.
摘要翻译：一种与具有场效应晶体管（FET）的开关一起使用的电路和方法和计算机程序产品。该方法和计算机程序产品包括将FET的漏极 - 源极电压限制在预定范围内; 然后切换FET。通常，一方面，本发明的特征在于具有源极，漏极和栅极端子的电路。电路包括具有耦合到漏极端子的第一漏极和耦合到源极端子的第一源极的第一FET; 第二FET，具有耦合到所述漏极端子的第二漏极和耦合到所述源极端子的第二源极; 以及耦合到所述栅极端子，所述第一栅极和所述第二栅极的控制电路。

10. 发明授权

US08455340B2 Method of fabricating heavily doped region in double-diffused source MOSFET (LDMOS) transistor 有权
标题翻译：在双扩散源MOSFET（LDMOS）晶体管中制造重掺杂区域的方法
公开(公告)号：US08455340B2
公开(公告)日：2013-06-04
申请号：US13184333
申请日：2011-07-15
申请人： Marco A. Zuniga , Budong You
发明人： Marco A. Zuniga , Budong You
IPC分类号： H01L21/425 , H01L21/336 , H01L21/04
CPC分类号： H01L21/041 , H01L21/823807 , H01L21/823814 , H01L27/0922 , H01L29/0696 , H01L29/086 , H01L29/0865 , H01L29/66689 , H01L29/7816 , H01L29/7836
摘要： A transistor includes a source, a drain and a gate. The source includes a p-doped p-body, a p+ region overlapping the p-body, an n+ region overlapping the p-body in proximity to the p+ region, and an n-doped source, heavily double-diffused (SHDD) region, only into the source region of the transistor, the SHDD region having a depth about equal to that of the first n+ region and overlapping the first n+ region. The drain includes a second n+ region and an n-doped shallow drain overlapping the second n+ region. The gate includes a gate oxide and a conductive material over the gate oxide. The SHDD region extends further laterally than the first n+ region beneath the gate oxide. The SHDD region is implanted using a dopant concentration greater than that of the n-doped shallow drain but less than that of the first n+ region.
摘要翻译：晶体管包括源极，漏极和栅极。源包括p掺杂p体，与p体重叠的p +区，与p +区相邻的p体重叠的n +区，以及n掺杂源，重双扩散（SHDD）区仅在晶体管的源极区域中，SHDD区域的深度大约等于第一n +区域的深度并且与第一n +区域重叠。漏极包括与第二n +区重叠的第二n +区和n掺杂的浅漏极。栅极包括栅极氧化物和栅极氧化物上的导电材料。 SHDD区域比栅极氧化物下面的第一n +区域进一步横向延伸。使用大于n掺杂浅漏极的掺杂浓度的掺杂浓度注入SHDD区，但是小于第一n +区的杂质浓度。

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