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1. 发明授权

US06751700B2 Date processor and storage system including a set associative cache with memory aliasing 失效
标题翻译：日期处理器和存储系统，包括具有存储器混叠的集合关联高速缓存
公开(公告)号：US06751700B2
公开(公告)日：2004-06-15
申请号：US09822244
申请日：2001-04-02
申请人： Bryan J Donoghue , Lee C Harrison , Edward Turner , Tin Lam , Victoria A Griffiths
发明人： Bryan J Donoghue , Lee C Harrison , Edward Turner , Tin Lam , Victoria A Griffiths
IPC分类号： G06F1200
CPC分类号： G06F12/0835 , G06F12/0864
摘要： A data processor and storage system which comprises a data processor, a cache memory and a main memory is arranged so that the addressing of the main memory produces a multiplicity of spaced aliases, the multiplicity being greater than the set-associativity of the cache memory. The cache memory may be a multiple way set associative cache memory with the system including a round robin allocator for controlling the storing of successive data items in the different ways of the set associative cache. The cache may also be a direct mapped cache having single way set-associativity so that the round robin allocator is not required. The system may also include a direct memory access (DMA) device for copying data items into the memory. The memory may be a buffer memory which is divided into a plurality of packet buffers.
摘要翻译：包括数据处理器，高速缓冲存储器和主存储器的数据处理器和存储系统被布置成使得主存储器的寻址产生多个间隔的别名，多重性大于高速缓存存储器的集合关联性。高速缓冲存储器可以是多路集相关高速缓冲存储器，其中该系统包括循环分配器，用于以不同的方式对该组关联高速缓存存储连续的数据项。高速缓存还可以是具有单向集合关联性的直接映射高速缓存，从而不需要循环分配器。该系统还可以包括用于将数据项复制到存储器中的直接存储器访问（DMA）设备。存储器可以是被分成多个分组缓冲器的缓冲存储器。

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