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1. 发明授权

US5392910A Package for a device having a sharp cutting edge 失效
标题翻译：具有尖锐切削刃的装置的包装
公开(公告)号：US5392910A
公开(公告)日：1995-02-28
申请号：US278131
申请日：1994-07-21
申请人： Bruce M. Bell , Steven W. Butler
发明人： Bruce M. Bell , Steven W. Butler
IPC分类号： A61B17/14 , A61B17/32 , A61B19/02 , B65D81/00
CPC分类号： B65D81/00 , A61B50/3001 , A61B50/33 , A61B17/14 , A61B17/142 , A61B17/3215
摘要： A package for a device having a sharp cutting edge, such as a bone saw, includes a tray having a bottom surface, a top surface and side walls. The side walls are connected between the bottom surface and the top surface. The top surface includes an upwardly facing central recessed portion for engaging a device such as a bone saw. The tray defines a downwardly facing recessed area adjacent the central portion. A protective strip of cushioning material is disposed within the downwardly facing recessed area and extends above and below the central portion. The protective strip prevents the device from engaging the side walls and is formed of a plastic sponge material which is soft, resilient and tear-resistant. A cover secured to the bottom surface of the tray retains the protective strip in operative position.
摘要翻译：用于具有尖锐切割边缘的装置（例如骨锯）的包装包括具有底面，顶面和侧壁的托盘。侧壁连接在底面和顶面之间。顶表面包括用于接合诸如骨锯的装置的面向上的中心凹部。托盘限定了邻近中心部分的面向下的凹陷区域。缓冲材料的保护带设置在向下的凹陷区域内并且在中心部分的上方和下方延伸。保护带防止装置与侧壁接合并且由柔软，有弹性和抗撕裂的塑料海绵材料形成。固定在托盘的底表面上的盖将保护带保持在操作位置。

2. 发明授权

US08271233B2 Method of multi-level fault isolation design 有权
标题翻译：多层次故障隔离设计方法
公开(公告)号：US08271233B2
公开(公告)日：2012-09-18
申请号：US12060397
申请日：2008-04-01
申请人： Steven W. Butler
发明人： Steven W. Butler
IPC分类号： G06F11/30
CPC分类号： F02K3/06 , F01D21/003 , F01D21/02 , F01D21/12 , F01D21/14 , F01D21/20
摘要： A fault isolation method and system includes tailored fault isolators for each grouping of similar data to differentiate between one or several potential faults within any group.
摘要翻译：故障隔离方法和系统包括用于每个分组相似数据的定制故障隔离器，以区分任何组内的一个或多个潜在故障。

3. 发明申请

US20140222310A1 ENGINE MONITOR FOR A MULTI-ENGINE SYSTEM 审中-公开
标题翻译：发动机监控系统
公开(公告)号：US20140222310A1
公开(公告)日：2014-08-07
申请号：US13647964
申请日：2012-10-09
申请人： Allan J. Volponi , Steven W. Butler
发明人： Allan J. Volponi , Steven W. Butler
IPC分类号： G01M15/04
CPC分类号： G01M15/04 , F02C6/00 , F02C9/00 , F05D2260/80
摘要： An engine monitor includes a first tuned modeling unit, a second tuned modeling unit and a monitoring unit. The first tuned modeling unit models dynamics of a first engine by processing first control data with a first engine model to provide modeled first engine parameter data, and at least partially adjusts the modeled first engine parameter data for model error in the first engine model to provide first tuned parameter data. The second tuned modeling unit models dynamics of a second engine by processing second control data with a second engine model to provide modeled second engine parameter data, and at least partially adjusts the modeled second engine parameter data for model error in the second engine model to provide second tuned parameter data. The monitoring unit correlates the first and the second tuned parameter data to monitor operation of the first and the second engines.
摘要翻译：引擎监视器包括第一调谐建模单元，第二调谐建模单元和监视单元。第一调谐建模单元通过利用第一发动机模型处理第一控制数据来提供第一引擎参数数据来模拟第一引擎的动力学，并且至少部分地调整用于第一引擎模型中的模型误差的建模的第一引擎参数数据，以提供首先调谐参数数据。第二调谐建模单元通过用第二发动机模型处理第二控制数据来模拟第二发动机的动力学来提供建模的第二发动机参数数据，并且至少部分地调整用于第二发动机模型中的模型误差的建模的第二发动机参数数据，以提供第二调谐参数数据。监测单元将第一和第二调谐参数数据相关联以监测第一和第二发动机的操作。

4. 发明申请

US20090248363A1 METHOD OF MULTI-LEVEL FAULT ISOLATION DESIGN 有权
标题翻译：多级故障隔离设计方法
公开(公告)号：US20090248363A1
公开(公告)日：2009-10-01
申请号：US12060397
申请日：2008-04-01
申请人： Steven W. Butler
发明人： Steven W. Butler
IPC分类号： G06F15/00
CPC分类号： F02K3/06 , F01D21/003 , F01D21/02 , F01D21/12 , F01D21/14 , F01D21/20
摘要： A fault isolation method and system includes tailored fault isolators for each grouping of similar data to differentiate between one or several potential faults within any group.
摘要翻译：故障隔离方法和系统包括用于每个分组相似数据的定制故障隔离器，以区分任何组内的一个或多个潜在故障。

5. 发明授权

US5495447A Method and apparatus using mapped redundancy to perform multiple large block memory array repair 失效
标题翻译：使用映射冗余来执行多个大块存储器阵列修复的方法和装置
公开(公告)号：US5495447A
公开(公告)日：1996-02-27
申请号：US342405
申请日：1994-11-18
申请人： Steven W. Butler , Hamid Partovi
发明人： Steven W. Butler , Hamid Partovi
IPC分类号： G11C8/12 , G11C29/00 , G11C7/00
CPC分类号： G11C29/804 , G11C29/808 , G11C8/12
摘要： A semiconductor memory device according to the invention includes a main memory comprising a number of memory sub-arrays, each coupled to an address and a data bus, for providing or receiving data to an intermediate interface unit. The intermediate interface unit provides data to and receives data from an output bus. Also included in the semiconductor memory device is redundancy circuit including a redundant memory coupled to the output bus for storing a subset of data from one of the sub-arrays in the event that the sub-array is defective. The redundancy circuit additionally includes address fuses for storing the sub-array addresses of the subset of data to be stored in the redundant storage, and compare circuitry coupled to the address bus for comparing the address bus to the stored array addresses to determine if there is a match. In the event of a match, the compare circuitry provides an index to the redundant storage unit and enables it to provide data to or receive data from the output bus, while precluding the intermediate interface from providing data from the main memory array to the output bus.
摘要翻译：根据本发明的半导体存储器件包括主存储器，其包括多个存储器子阵列，每个存储器子阵列耦合到地址和数据总线，用于向中间接口单元提供或接收数据。中间接口单元向输出总线提供数据和从输出总线接收数据。还包括在半导体存储器件中的冗余电路包括耦合到输出总线的冗余存储器，用于在子阵列有缺陷的情况下存储来自子阵列之一的数据子集。冗余电路还包括用于存储要存储在冗余存储器中的数据子集的子阵列地址的地址熔丝，以及耦合到地址总线的比较电路，用于将地址总线与存储的阵列地址进行比较，以确定是否存在一场比赛在匹配的情况下，比较电路为冗余存储单元提供索引，并使其能够向输出总线提供数据或从输出总线接收数据，同时阻止中间接口从主存储器阵列向输出总线提供数据。

6. 发明授权

US5378945A Voltage level converting buffer circuit 失效
标题翻译：电压电平转换缓冲电路
公开(公告)号：US5378945A
公开(公告)日：1995-01-03
申请号：US97781
申请日：1993-07-26
申请人： Hamid Partovi , Steven W. Butler , Laun Q. Tran
发明人： Hamid Partovi , Steven W. Butler , Laun Q. Tran
IPC分类号： H03K19/003 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/00315 , H03K19/018521
摘要： A voltage level conversion buffer circuit including a first and a second transistor each having a gate, a drain, and a source. The drain of the first transistor and the gate of the second transistor are connected together to provide an input to the buffer circuit, and the gate of the first transistor and the drain of the second transistor are connected to a supply voltage. The sources of the first and second transistors are connected together to provide an output for the buffer circuit.
摘要翻译：一种电压电平转换缓冲电路，包括具有栅极，漏极和源极的第一和第二晶体管。第一晶体管的漏极和第二晶体管的栅极连接在一起，以向缓冲电路提供输入，第一晶体管的栅极和第二晶体管的漏极连接到电源电压。第一和第二晶体管的源极连接在一起以提供缓冲电路的输出。

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