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1. 发明申请

US20120058615A1 Method of Forming Shielded Gate Power Transistor Utilizing Chemical Mechanical Planarization 有权
标题翻译：使用化学机械平面化形成屏蔽栅极功率晶体管的方法
公开(公告)号：US20120058615A1
公开(公告)日：2012-03-08
申请号：US13042292
申请日：2011-03-07
申请人： Bruce Douglas Marchant , Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
发明人： Bruce Douglas Marchant , Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
摘要翻译：形成屏蔽栅场效应晶体管的方法包括：在硅区中形成多个有源栅极沟槽; 用屏蔽电介质衬套有源栅极沟槽的下侧壁和底部; 使用CMP工艺，用包括多晶硅的屏蔽电极填充有源栅极沟槽的底部; 在所述有源栅极沟槽中的所述屏蔽电极上形成多层间介电层（IPD）; 用栅极电介质衬套有源栅极沟槽的上侧壁; 以及在有源栅极沟槽的上部在IPD上形成栅电极。

2. 发明授权

US07449354B2 Trench-gated FET for power device with active gate trenches and gate runner trench utilizing one-mask etch 失效
标题翻译：利用化学机械平面化的功率器件
公开(公告)号：US07449354B2
公开(公告)日：2008-11-11
申请号：US11327657
申请日：2006-01-05
申请人： Bruce Douglas Marchant , Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
发明人： Bruce Douglas Marchant , Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
IPC分类号： H01L21/00
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A trench-gated field effect transistor (FET) is formed as follows. Using one mask, a plurality of active gate trenches and at least one gate runner trench are defined and simultaneously formed in a silicon region such that (i) the at least one gate runner trench has a width greater than a width of each of the plurality of active gate trenches, and (ii) the plurality of active gate trenches are contiguous with the at least one gate runner trench.
摘要翻译：沟槽门控场效应晶体管（FET）如下形成。使用一个掩模，多个有源栅极沟槽和至少一个栅极流道沟槽被限定并同时形成在硅区域中，使得（i）至少一个栅极流道沟槽的宽度大于多个栅极沟槽的宽度的有源栅极沟槽，以及（ii）多个有源栅极沟槽与至少一个栅极流道沟槽邻接。

3. 发明授权

US08461040B2 Method of forming shielded gate power transistor utilizing chemical mechanical planarization 有权
标题翻译：使用化学机械平面化形成屏蔽栅极功率晶体管的方法
公开(公告)号：US08461040B2
公开(公告)日：2013-06-11
申请号：US13042292
申请日：2011-03-07
申请人： Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
发明人： Thomas E. Grebs , Rodney S. Ridley , Nathan Lawrence Kraft
IPC分类号： H01L21/4763
CPC分类号： H01L29/7811 , H01L21/3083 , H01L29/0696 , H01L29/407 , H01L29/42368 , H01L29/4238 , H01L29/7813 , Y10S438/942 , Y10S438/95
摘要： A method of forming a shielded gate field effect transistor includes: forming a plurality of active gate trenches in a silicon region; lining lower sidewalls and bottom of the active gate trenches with a shield dielectric; using a CMP process, filling a bottom portion of the active gate trenches with a shield electrode comprising polysilicon; forming an interpoly dielectric (IPD) over the shield electrode in the active gate trenches; lining upper sidewalls of the active gate trenches with a gate dielectric; and forming a gate electrode over the IPD in an upper portion of the active gate trenches.
摘要翻译：形成屏蔽栅场效应晶体管的方法包括：在硅区中形成多个有源栅极沟槽; 用屏蔽电介质衬套有源栅极沟槽的下侧壁和底部; 使用CMP工艺，用包括多晶硅的屏蔽电极填充有源栅极沟槽的底部; 在所述有源栅极沟槽中的所述屏蔽电极上形成多层间介电层（IPD）; 用栅极电介质衬套有源栅极沟槽的上侧壁; 以及在有源栅极沟槽的上部在IPD上形成栅电极。

4. 发明授权

US06818947B2 Buried gate-field termination structure 有权
标题翻译：埋地栅场终端结构
公开(公告)号：US06818947B2
公开(公告)日：2004-11-16
申请号：US10247464
申请日：2002-09-19
申请人： Thomas E. Grebs , Christopher B. Kocon , Rodney S. Ridley, Sr. , Gary M. Dolny , Nathan Lawrence Kraft , Louise E. Skurkey
发明人： Thomas E. Grebs , Christopher B. Kocon , Rodney S. Ridley, Sr. , Gary M. Dolny , Nathan Lawrence Kraft , Louise E. Skurkey
IPC分类号： H01L2976
CPC分类号： H01L29/7813 , H01L29/402 , H01L29/407 , H01L29/4232 , H01L29/4238 , H01L29/7397 , H01L29/7811
摘要： In a power semiconductor device 10, a continuous trench has an outer circumferential portion 58 that includes a field plate and inner portions 28 that carry include one or more gate runners 34 to that the gate runners and the field plate are integral with each other. The trench structure 58, 28 is simpler to form and takes up less surface space that the separate structures of the prior art. The trench is lined with an insulator and further filled with conductive polysilicon and a top insulator.
摘要翻译：在功率半导体器件10中，连续沟槽具有包括场板的外周部58和承载包括一个或多个栅极流道34的内部部分28，使得栅极流道和场板彼此成一体。沟槽结构58,28更容易形成和占据现有技术的分离结构的较小的表面空间。沟槽衬有绝缘体，并进一步填充导电多晶硅和顶绝缘体。

5. 发明授权

US07935577B2 Method for forming shielded gate field effect transistor using spacers 有权
标题翻译：用间隔物形成屏蔽栅场效应晶体管的方法
公开(公告)号：US07935577B2
公开(公告)日：2011-05-03
申请号：US12344859
申请日：2008-12-29
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
IPC分类号： H01L21/8232 , H01L21/84 , H01L21/00 , H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.
摘要翻译：在半导体区域中形成沟槽。形成在沟槽的侧壁和底表面上的介电层。电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。在形成电介质层之后，沟槽的下部填充有屏蔽电极。电介质间隔物沿着上沟槽侧壁形成。在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。在形成IED之后，去除电介质间隔物。

6. 发明授权

US07476589B2 Methods for forming shielded gate field effect transistors 有权
标题翻译：形成屏蔽栅场效应晶体管的方法
公开(公告)号：US07476589B2
公开(公告)日：2009-01-13
申请号：US11479117
申请日：2006-06-29
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley
IPC分类号： H01L21/336 , H01L21/4763
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A field effect transistor is formed as follows. A trench is formed in a semiconductor region. A dielectric layer lining the trench sidewalls and bottom is formed. The trench is filled with a conductive material. The conductive material is recessed into the trench to thereby form a shield electrode in a bottom portion of the trench. The recessing of the conductive material includes isotropic etching of the conductive material. An inter-electrode dielectric (IED) is formed over the recessed shield electrode.
摘要翻译：场效应晶体管如下形成。在半导体区域中形成沟槽。形成衬在沟槽侧壁和底部的电介质层。沟槽填充有导电材料。导电材料凹陷到沟槽中，从而在沟槽的底部形成屏蔽电极。导电材料的凹陷包括导电材料的各向同性蚀刻。在凹形屏蔽电极上形成电极间电介质（IED）。

7. 发明授权

US08803207B2 Shielded gate field effect transistors 有权
标题翻译：屏蔽栅场效应晶体管
公开(公告)号：US08803207B2
公开(公告)日：2014-08-12
申请号：US13081400
申请日：2011-04-06
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
IPC分类号： H01L29/76 , H01L29/66
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： In one general aspect, an apparatus can include a trench disposed in a semiconductor region, a shield dielectric layer lining a lower portion of a sidewall of the trench and a bottom surface of the trench, and a gate dielectric lining a upper portion of the sidewall of the trench. The apparatus can also include a shield electrode disposed in a lower portion of the trench and insulated from the semiconductor region by the shield dielectric layer, and an inter-electrode dielectric (IED) disposed in the trench over the shield electrode where the shield electrode has a curved top surface.
摘要翻译：在一个一般方面，一种装置可以包括设置在半导体区域中的沟槽，衬在沟槽的侧壁的下部的屏蔽电介质层和沟槽的底表面，以及衬在该侧壁的上部的栅极电介质的沟槽。该设备还可以包括设置在沟槽的下部并由屏蔽电介质层与半导体区域绝缘的屏蔽电极，以及设置在屏蔽电极上的沟槽中的电极间电介质（IED），其中屏蔽电极具有一个弯曲的顶面。

8. 发明申请

US20110212586A1 Method for Forming Shielded Gate Field Effect Transistors 有权
标题翻译：屏蔽栅场效应晶体管形成方法
公开(公告)号：US20110212586A1
公开(公告)日：2011-09-01
申请号：US13081400
申请日：2011-04-06
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
IPC分类号： H01L21/336 , H01L21/3205
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A method for forming a field effect transistor includes forming a trench in a semiconductor region and forming a dielectric layer lining lower sidewalls and bottom surface of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. An inter-electrode dielectric (IED) is formed in the trench over the shield electrode by carrying out a steam ambient oxidation and carrying out a dry ambient oxidation. A gate electrode is formed in an upper portion of the trench. The gate electrode may be insulated from the shield electrode by the IED.
摘要翻译：用于形成场效应晶体管的方法包括在半导体区域中形成沟槽，并形成衬在沟槽的下侧壁和底表面的电介质层。在形成电介质层之后，沟槽的下部填充有屏蔽电极。通过进行蒸汽环境氧化并进行干燥环境氧化，在屏蔽电极上的沟槽中形成电极间电介质（IED）。栅电极形成在沟槽的上部。栅电极可以通过IED与屏蔽电极绝缘。

9. 发明申请

US20090111231A1 Method for Forming Shielded Gate Field Effect Transistor Using Spacers 有权
标题翻译：用隔板形成屏蔽栅场效应晶体管的方法
公开(公告)号：US20090111231A1
公开(公告)日：2009-04-30
申请号：US12344859
申请日：2008-12-29
申请人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
发明人： Thomas E. Grebs , Nathan Lawrence Kraft , Rodney Ridley , Gary M. Dolny , Joseph A. Yedinak , Christopher Boguslaw Kocon , Ashok Challa
IPC分类号： H01L21/336
CPC分类号： H01L29/7813 , H01L21/26586 , H01L29/0865 , H01L29/0869 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/42376 , H01L29/66719 , H01L29/66727 , H01L29/66734 , H01L29/7811
摘要： A trench is formed in a semiconductor region. A dielectric layer lining sidewalls and bottom surface of the trench is formed. The dielectric layer is thicker along lower sidewalls and the bottom surface than along upper sidewalls of the trench. After forming the dielectric layer, a lower portion of the trench is filled with a shield electrode. Dielectric spacers are formed along the upper trench sidewalls. After forming the dielectric spacers, an inter-electrode dielectric (IED) is formed in the trench over the shield electrode. After forming the IED, the dielectric spacers are removed.
摘要翻译：在半导体区域中形成沟槽。形成在沟槽的侧壁和底表面上的介电层。电介质层沿着下侧壁和底表面比沿着沟槽的上侧壁更厚。在形成电介质层之后，沟槽的下部填充有屏蔽电极。电介质间隔物沿着上沟槽侧壁形成。在形成电介质间隔物之后，在屏蔽电极上的沟槽中形成电极间电介质（IED）。在形成IED之后，去除电介质间隔物。

10. 发明授权

US07452777B2 Self-aligned trench MOSFET structure and method of manufacture 有权
标题翻译：自对准沟槽MOSFET结构及其制造方法
公开(公告)号：US07452777B2
公开(公告)日：2008-11-18
申请号：US11339998
申请日：2006-01-25
申请人： Christopher Boguslaw Kocon , Nathan Lawrence Kraft
发明人： Christopher Boguslaw Kocon , Nathan Lawrence Kraft
IPC分类号： H01L21/336
CPC分类号： H01L29/7811 , H01L29/0661 , H01L29/407 , H01L29/41766 , H01L29/4236 , H01L29/42368 , H01L29/66727 , H01L29/66734 , H01L29/7813
摘要： A trench gate FET is formed as follows. A well region is formed in a silicon region. A plurality of active gate trenches and a termination trench are simultaneously formed in an active region and a termination region of the FET, respectively, such that the well region is divided into a plurality of active body regions and a termination body region. Using a mask, openings are formed over the termination body region and the active body region. Dopants are implanted into the active body regions and the termination body region through the openings thereby forming a first region in each active and termination body region. Exposed surfaces of all first regions are recessed so as to form a bowl-shaped recess having slanted walls and a bottom protruding through the first region such that remaining portions of the first region in each active body region form source regions that are self-aligned to the active gate trenches.
摘要翻译：沟槽栅FET如下形成。阱区域形成在硅区域中。多个有源栅极沟槽和端接沟槽分别同时形成在FET的有源区域和端接区域中，使得阱区域被分成多个有源体区域和端接体区域。使用掩模，在终端体区域和活动体区域上形成开口。通过开口将掺杂剂注入活性体区域和终端体区域，从而在每个活性和终止体区域中形成第一区域。所有第一区域的露出的表面是凹进的，从而形成具有倾斜壁和通过第一区域突出的底部的碗状凹部，使得每个活性体区域中的第一区域的剩余部分形成自对准的源区域有源栅极沟槽。

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