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1. 发明申请

US20050127362A1 Sectional field effect devices and method of fabrication 有权
标题翻译：截面场效应器件及其制造方法
公开(公告)号：US20050127362A1
公开(公告)日：2005-06-16
申请号：US10732322
申请日：2003-12-10
申请人： Ying Zhang , Bruce Doris , Thomas Kanarsky , Meikei Ieong , Jakub Kedzierski
发明人： Ying Zhang , Bruce Doris , Thomas Kanarsky , Meikei Ieong , Jakub Kedzierski
IPC分类号： H01L29/812 , H01L21/335 , H01L21/336 , H01L21/338 , H01L29/423 , H01L29/786 , H01L29/76
CPC分类号： H01L29/785 , H01L29/42384 , H01L29/66795
摘要： A field effect device is disclosed which has a body formed of a crystalline semiconductor material and has at least one vertically oriented section and at least one horizontally oriented section. The device is produced in SOI technology by fabricating first a formation of the device in masking insulators, and then transferring this formation through several etching steps into the SOI layer. The segmented field effect device combines FinFET, or fully depleted silicon-on-insulator FETs, type devices with fully depleted planar devices. This combination allows device width control with FinFET type devices. The segmented field effect device gives high current drive for a given layout area. The segmented field effect devices allow for the fabrication of high performance processors.
摘要翻译：公开了一种场效应器件，其具有由晶体半导体材料形成的主体，并具有至少一个垂直取向部分和至少一个水平定向部分。该器件通过在掩模绝缘体中首先制造器件的形成，然后将该形成通过几个蚀刻步骤转移到SOI层中而以SOI技术制造。分段场效应器件结合FinFET或完全耗尽的绝缘体上硅FET，具有完全耗尽的平面器件的类型器件。该组合允许使用FinFET类型器件进行器件宽度控制。分段场效应器件为给定的布局区域提供高电流驱动。分段场效应器件允许制造高性能处理器。

2. 发明申请

US20050263831A1 Hybrid planar and FinFET CMOS devices 有权
标题翻译：混合平面和FinFET CMOS器件
公开(公告)号：US20050263831A1
公开(公告)日：2005-12-01
申请号：US11122193
申请日：2005-05-04
申请人： Bruce Doris , Diane Boyd , Meikei Ieong , Thomas Kanarsky , Jakub Kedzierski , Min Yang
发明人： Bruce Doris , Diane Boyd , Meikei Ieong , Thomas Kanarsky , Jakub Kedzierski , Min Yang
IPC分类号： H01L29/423 , H01L21/336 , H01L21/8234 , H01L21/84 , H01L27/08 , H01L27/088 , H01L27/12 , H01L29/49 , H01L29/786 , H01L31/113
CPC分类号： H01L27/1211 , H01L21/845 , H01L29/66795 , H01L29/785
摘要： The present invention provides an integrated semiconductor circuit containing a planar single gated FET and a FinFET located on the same SOI substrate. Specifically, the integrated semiconductor circuit includes a FinFET and a planar single gated FET located atop a buried insulating layer of an silicon-on-insulator substrate, the planar single gated FET is located on a surface of a patterned top semiconductor layer of the silicon-on-insulator substrate and the FinFET has a vertical channel that is perpendicular to the planar single gated FET. A method of forming a method such an integrated circuit is also provided. In the method, resist imaging and a patterned hard mask are used in trimming the width of the FinFET active device region and subsequent resist imaging and etching are used in thinning the thickness of the FET device area. The trimmed active FinFET device region is formed such that it lies perpendicular to the thinned planar single gated FET device region.
摘要翻译：本发明提供一种集成半导体电路，其包含位于同一SOI衬底上的平面单栅极FET和FinFET。具体地，集成半导体电路包括FinFET和位于绝缘体上硅衬底的掩埋绝缘层顶上的平面单栅极FET，平面单门控FET位于硅 - 硅绝缘体的图案化顶部半导体层的表面上，绝缘体上的衬底和FinFET具有垂直于平面单门控FET的垂直沟道。还提供了一种形成集成电路的方法。在该方法中，抗蚀剂成像和图案化的硬掩模用于修整FinFET有源器件区域的宽度，并且随后的抗蚀剂成像和蚀刻用于减薄FET器件区域的厚度。经修整的有源FinFET器件区域形成为垂直于薄化的平面单栅极FET器件区域。

3. 发明申请

US20050127408A1 Ultra-thin Si channel CMOS with improved series resistance 有权
标题翻译：超薄Si沟道CMOS，具有改善的串联电阻
公开(公告)号：US20050127408A1
公开(公告)日：2005-06-16
申请号：US10735736
申请日：2003-12-16
申请人： Bruce Doris , Meikei Ieong , Thomas Kanarsky
发明人： Bruce Doris , Meikei Ieong , Thomas Kanarsky
IPC分类号： H01L21/8238 , H01L21/84 , H01L27/12 , H01L21/336 , H01L29/76 , H01L31/062 , H01L31/119
CPC分类号： H01L27/1203 , H01L21/823814 , H01L21/84
摘要： Thin silicon channel SOI devices provide the advantage of sharper sub-threshold slope, high mobility, and better short-channel effect control but exhibit a typical disadvantage of increased series resistance. This high series resistance is avoided by using a raised source-drain (RSD), and expanding the source drain on the pFET transistor in the CMOS pair using selective epitaxial Si growth which is decoupled between nFETs and pFETs. By doing so, the series resistance is improved, the extensions are implanted after RSD formation and thus not exposed to the high thermal budget of the RSD process while the pFET and nFET can achieve independent effective offsets.
摘要翻译：薄硅沟道SOI器件具有更清晰的子阈值斜率，高迁移率和更好的短沟道效应控制的优点，但呈现增加串联电阻的典型缺点。通过使用升高的源极 - 漏极（RSD）和使用在nFET和pFET之间去耦合的选择性外延Si生长来扩展CMOS对中的pFET晶体管上的源极漏极来避免该高串联电阻。通过这样做，串联电阻得到改善，扩展在RSD形成后植入，因此不暴露于RSD工艺的高热预算，而pFET和nFET可以实现独立的有效偏移。

4. 发明申请

US20050048752A1 Ultra thin channel MOSFET 有权
标题翻译：超薄通道MOSFET
公开(公告)号：US20050048752A1
公开(公告)日：2005-03-03
申请号：US10650229
申请日：2003-08-28
申请人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/3205
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.
摘要翻译：描述了制造薄沟道硅绝缘体上结构的方法。本发明的方法包括在第一装置和第二装置区域中形成邻接栅极区的一组薄间隔件; 在第一器件区域和第二器件区域中的栅极区域的任一侧上形成凸起的源极/漏极区域，将第一导电类型的掺杂剂注入到第一器件区域中的凸起的源极漏极区域中以形成第一掺杂剂杂质区域，其中所述第二设备区域被第二设备区域块掩码保护; 将第二导电类型的掺杂剂注入所述第二器件区域中的所述升高的源极/漏极区域中以形成第二掺杂剂杂质区域，其中所述第一器件区域被第一器件区域阻挡掩模保护; 以及激活第一掺杂杂质区和第二掺杂杂质区，以提供薄沟道MOSFET。

5. 发明申请

US20050003589A1 Structure and method to fabricate ultra-thin Si channel devices 审中-公开
公开(公告)号：US20050003589A1
公开(公告)日：2005-01-06
申请号：US10862073
申请日：2004-06-04
申请人： Bruce Doris , Thomas Kanarsky , Meikei Ieong , Wesley Natzle
发明人： Bruce Doris , Thomas Kanarsky , Meikei Ieong , Wesley Natzle
IPC分类号： H01L21/762 , H01L21/84 , H01L31/0392
CPC分类号： H01L21/84 , H01L21/76283
摘要： A method for preventing polysilicon stringer formation under the active device area of an isolated ultra-thin Si channel device is provided. The method utilizes a chemical oxide removal (COR) processing step to prevent stinger formation, instead of a conventional wet etch process wherein a chemical etchant such as HF is employed. A silicon-on-insulator (SOI) structure is also provided. The structure includes at least a top Si-containing layer located on a buried insulating layer; and an oxide filled trench isolation region located in the top Si-containing layer and a portion of the buried insulating layer. No undercut regions are located beneath the top Si-containing layer.

6. 发明申请

US20050164433A1 Ultra thin channel MOSFET 失效
公开(公告)号：US20050164433A1
公开(公告)日：2005-07-28
申请号：US11083743
申请日：2005-03-18
申请人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
发明人： Bruce Doris , Thomas Kanarsky , Ying Zhang , Huilong Zhu , Meikei Ieong , Omer Dokumaci
IPC分类号： H01L21/336 , H01L21/84 , H01L27/12 , H01L29/786 , H01L21/00
CPC分类号： H01L29/66772 , H01L21/84 , H01L27/1203 , H01L29/6656 , H01L29/78612 , H01L29/78621
摘要： Described is a method for making thin channel silicon-on-insulator structures. The inventive method comprises forming a set of thin spacer abutting a gate region in a first device and a second device region; forming a raised source/drain region on either side of the gate region in the first device region and the second device region, implanting dopants of a first conductivity type into the raised source drain region in the first device region to form a first dopant impurity region, where the second device region is protected by a second device region block mask; implanting dopants of a second conductivity type into the raised source/drain region in the second device region to form a second dopant impurity region, where the first device region is protected by a first device region block mask; and activating the first dopant impurity region and the second dopant impurity region to provide a thin channel MOSFET.

7. 发明申请

US20070170507A1 STRUCTURE AND METHOD FOR MANUFACTURING PLANAR STRAINED Si/SiGe SUBSTRATE WITH MULTIPLE ORIENTATIONS AND DIFFERENT STRESS LEVELS 审中-公开
标题翻译：用于制造具有多个方位和不同应力水平的平面应变Si / SiGe衬底的结构和方法
公开(公告)号：US20070170507A1
公开(公告)日：2007-07-26
申请号：US11693377
申请日：2007-03-29
申请人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
发明人： Huilong Zhu , Bruce Doris , Philip Oldiges , Meikei Ieong , Min Yang , Huajie Chen
IPC分类号： H01L27/12 , H01L27/01 , H01L31/0392
CPC分类号： H01L27/1203 , H01L21/823807 , H01L21/84 , H01L27/1207 , Y10S438/938
摘要： The present invention provides a method of forming a semiconducting substrate including the steps of providing an initial structure having first device region comprising a first orientation material and a second device region having a second orientation material; forming a first concentration of lattice modifying material atop the first orientation material; forming a second concentration of the lattice modifying material atop the second orientation material; intermixing the first concentration of lattice modifying material with the first orientation material to produce a first lattice dimension surface and the second concentration of lattice modifying material the second orientation material to produce a second lattice dimension surface; and forming a first strained semiconducting layer atop the first lattice dimension surface and a second strained semiconducting layer atop the second lattice dimension surface.
摘要翻译：本发明提供一种形成半导体衬底的方法，包括以下步骤：提供具有包括第一取向材料的第一器件区域和具有第二取向材料的第二器件区域的初始结构; 在所述第一取向材料的顶部上形成晶格改性材料的第一浓度; 在所述第二取向材料的顶部上形成所述晶格改性材料的第二浓度; 将所述晶格修饰材料的第一浓度与所述第一取向材料混合以产生第一晶格尺寸表面，并且所述第二浓度的晶格修饰材料形成所述第二取向材料以产生第二晶格尺寸表面; 以及在所述第一晶格尺寸表面上方形成第一应变半导体层和在所述第二晶格尺寸表面顶部形成第二应变半导体层。

8. 发明申请

US20070063278A1 HIGHLY MANUFACTURABLE SRAM CELLS IN SUBSTRATES WITH HYBRID CRYSTAL ORIENTATION 有权
标题翻译：具有混合晶体取向的衬底中的高度可制造的SRAM电池
公开(公告)号：US20070063278A1
公开(公告)日：2007-03-22
申请号：US11162780
申请日：2005-09-22
申请人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
发明人： Bruce Doris , Gregory Costrini , Oleg Gluschenkov , Meikei Ieong , Nakgeuon Seong
IPC分类号： H01L27/12
CPC分类号： H01L27/1104 , H01L27/11 , Y10S257/903 , Y10S438/973
摘要： The present invention relates to a semiconductor device structure that includes at least one SRAM cell formed in a substrate. Such SRAM cell comprises two pull-up transistors, two pull-down transistors, and two pass-gate transistors. The pull-down transistors and the pass-gate transistors are substantially similar in channel widths and have substantially similar source-drain doping concentrations, while the SRAM cell has a beta ratio of at least 1.5. The substrate preferably comprises a hybrid substrate with at two isolated sets of regions, while carrier mobility in these two sets of regions differentiates by a factor of at least about 1.5. More preferably, the pull-down transistors of the SRAM cell are formed in one set of regions, and the pass-gate transistors are formed in the other set of regions, so that current flow in the pull-down transistors is larger than that in the pass-gate transistors.
摘要翻译：本发明涉及一种半导体器件结构，其包括在衬底中形成的至少一个SRAM单元。这样的SRAM单元包括两个上拉晶体管，两个下拉晶体管和两个通过栅极晶体管。下拉晶体管和栅极晶体管在沟道宽度上基本相似，并且具有基本相似的源极 - 漏极掺杂浓度，而SRAM单元的β比率至少为1.5。衬底优选地包括具有两个分离的区域集合的混合衬底，而这两组区域中的载流子迁移率以至少约1.5的因子差分。更优选地，SRAM单元的下拉晶体管形成在一组区域中，并且栅极晶体管形成在另一组区域中，使得下拉晶体管中的电流大于传输栅晶体管。

9. 发明申请

US20070246753A1 Metal gated ultra short MOSFET devices 有权
标题翻译：金属门极超短MOSFET器件
公开(公告)号：US20070246753A1
公开(公告)日：2007-10-25
申请号：US11407473
申请日：2006-04-20
申请人： Jack Chu , Bruce Doris , Meikei Ieong , Jing Wang
发明人： Jack Chu , Bruce Doris , Meikei Ieong , Jing Wang
IPC分类号： H01L29/76
CPC分类号： H01L29/7838 , H01L21/28017 , H01L29/105
摘要： MOSFET devices suitable for operation at gate lengths less than about 40 nm, and methods of their fabrication is being presented. The MOSFET devices include a ground plane formed of a monocrystalline Si based material. A Si based body layer is epitaxially disposed over the ground plane. The body layer is doped with impurities of opposite type than the ground plane. The gate has a metal with a mid-gap workfunction directly contacting a gate insulator layer. The gate is patterned to a length of less than about 40 nm, and possibly less than 20 nm. The source and the drain of the MOSFET are doped with the same type of dopant as the body layer. In CMOS embodiments of the invention the metal in the gate of the NMOS and the PMOS devices may be the same metal.
摘要翻译：适用于栅极长度小于约40nm的MOSFET器件及其制造方法。 MOSFET器件包括由单晶Si基材料形成的接地平面。 Si基体层外延地设置在接地平面上。体层掺杂了与地平面相反的杂质。栅极具有中间功能函数的金属，其直接接触栅极绝缘体层。栅极被图案化成小于约40nm，并且可能小于20nm的长度。 MOSFET的源极和漏极掺杂有与体层相同类型的掺杂剂。在本发明的CMOS实施例中，NMOS和PMOS器件的栅极中的金属可以是相同的金属。

10. 发明申请

US20060237791A1 Ultra thin body fully-depleted SOI MOSFETs 有权
标题翻译：超薄体全耗尽SOI MOSFET
公开(公告)号：US20060237791A1
公开(公告)日：2006-10-26
申请号：US11473757
申请日：2006-06-23
申请人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
发明人： Bruce Doris , Meikei Ieong , Zhibin Ren , Paul Solomon , Min Yang
IPC分类号： H01L27/12
CPC分类号： H01L29/78696 , H01L29/66545 , H01L29/66772
摘要： A method of creating ultra thin body fully-depleted SOI MOSFETs in which the SOI thickness changes with gate-length variations thereby minimizing the threshold voltage variations that are typically caused by SOI thickness and gate-length variations is provided. The method of present invention uses a replacement gate process in which nitrogen is implanted to selectively retard oxidation during formation of a recessed channel. A self-limited chemical oxide removal (COR) processing step can be used to improve the control in the recessed channel step. If the channel is doped, the inventive method is designed such that the thickness of the SOI layer is increased with shorter channel length. If the channel is undoped or counter-doped, the inventive method is designed such that the thickness of the SOI layer is decreased with shorter channel length.
摘要翻译：提供了一种制造超薄体全耗尽SOI MOSFET的方法，其中SOI厚度随栅极长度变化而变化，从而最小化通常由SOI厚度和栅极长度变化引起的阈值电压变化。本发明的方法使用其中注入氮的替代浇口工艺，以便在形成凹陷通道期间选择性地延迟氧化。可以使用自限制化学氧化物去除（COR）处理步骤来改善凹陷通道步骤中的控制。如果沟道被掺杂，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的增加而增加。如果通道是未掺杂或反掺杂的，则本发明的方法被设计成使得SOI层的厚度随着沟道长度的减小而减小。

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