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1. 发明申请

US20060080513A1 Low latency coherency protocol for a multi-chip multiprocessor system 失效
公开(公告)号：US20060080513A1
公开(公告)日：2006-04-13
申请号：US10961751
申请日：2004-10-08
申请人： Bruce Beukema , Russell Hoover , Jon Kriegel , Eric Mejdrich , Sandra Woodward
发明人： Bruce Beukema , Russell Hoover , Jon Kriegel , Eric Mejdrich , Sandra Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828
摘要： Methods and apparatus for reducing the amount of latency involved when accessing, by a remote device, data residing in a cache of a processor are provided. For some embodiments, virtual channels may be utilized to conduct request/response transactions between the remote device and processor that satisfy a set of associated coherency rules.

2. 发明申请

US20070294481A1 SNOOP FILTER DIRECTORY MECHANISM IN COHERENCY SHARED MEMORY SYSTEM 审中-公开
标题翻译： SNOOP过滤器机密共享共享存储系统
公开(公告)号：US20070294481A1
公开(公告)日：2007-12-20
申请号：US11848960
申请日：2007-08-31
申请人： Russell Hoover , Eric Mejdrich , Jon Kriegel , Sandra Woodward
发明人： Russell Hoover , Eric Mejdrich , Jon Kriegel , Sandra Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译：提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。

3. 发明申请

US20060080508A1 Snoop filter directory mechanism in coherency shared memory system 失效
标题翻译： Snoop过滤器目录机制中的一致性共享内存系统
公开(公告)号：US20060080508A1
公开(公告)日：2006-04-13
申请号：US10961749
申请日：2004-10-08
申请人： Russell Hoover , Eric Mejdrich , Jon Kriegel , Sandra Woodward
发明人： Russell Hoover , Eric Mejdrich , Jon Kriegel , Sandra Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0835 , G06F12/0822 , G06F2212/302
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. Various mechanisms, such as a remote cache directory, castout buffer, and/or outstanding transaction buffer may be utilized by the remote device to track the state of processor cache lines that may hold data targeted by requests initiated by the remote device. Based on the content of these mechanisms, requests targeting data that is not in the processor cache may be routed directly to memory, thus reducing overall latency.
摘要翻译：提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。远程设备可以利用各种机制，诸如远程高速缓存目录，转储缓冲区和/或未完成的事务缓冲器来跟踪可以保存由远程设备发起的请求所针对的数据的处理器高速缓存行的状态。基于这些机制的内容，针对不在处理器高速缓存中的数据的请求可以直接路由到存储器，从而减少总体延迟。

4. 发明申请

US20060080511A1 Enhanced bus transactions for efficient support of a remote cache directory copy 审中-公开
标题翻译：增强总线事务，有效支持远程缓存目录副本
公开(公告)号：US20060080511A1
公开(公告)日：2006-04-13
申请号：US10961742
申请日：2004-10-08
申请人： Russell Hoover , Jon Kriegel , Eric Mejdrich , Sandra Woodward
发明人： Russell Hoover , Jon Kriegel , Eric Mejdrich , Sandra Woodward
IPC分类号： G06F12/00
CPC分类号： G06F12/0828 , G06F12/0833
摘要： Methods and apparatus are provided that may be utilized to maintain a copy of a processor cache directory on a remote device that may access data residing in a cache of the processor. Enhanced bus transactions containing cache coherency information used to maintain the remote cache directory may be automatically generated when the processor allocates or de-allocates cache lines. Rather than query the processor cache directory prior to each memory access to determine if the processor cache contains an updated copy of requested data, the remote device may query its remote copy.
摘要翻译：提供了可用于维护远程设备上可处理驻留在处理器的高速缓存中的数据的处理器高速缓存目录的副本的方法和装置。当处理器分配或取消分配高速缓存行时，可能会自动生成包含用于维护远程缓存目录的缓存一致性信息的增强总线事务。而不是在每个存储器访问之前查询处理器缓存目录，以确定处理器高速缓存是否包含所请求数据的更新副本，远程设备可以查询其远程副本。

5. 发明申请

US20060095672A1 System and method for parallel execution of data generation tasks 审中-公开
标题翻译：并行执行数据生成任务的系统和方法
公开(公告)号：US20060095672A1
公开(公告)日：2006-05-04
申请号：US11065343
申请日：2005-02-25
申请人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash , Russell Hoover , Eric Mejdrich , Sandra Woodward
发明人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Michael Abrash , Russell Hoover , Eric Mejdrich , Sandra Woodward
IPC分类号： G06F12/14
CPC分类号： G06F15/7846
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data. The amount of output data is greater than an amount of input data, and the ratio of the amount of input data to the amount of output data defines a decompression ratio. In one implementation, the high-level host-related task performed by the host element pertains to a high-level graphics processing task, and the data-generating task pertains to the generation of geometry data (such as triangle vertices) for use within the high-level graphics processing task. The CPU module can transfer the output data to a GPU module via at least one locked set of a cache memory. The GPU retrieves the output data from the locked set, and periodically forwards a tail pointer to a cacheable location within the data-generating elements that informs the data-generating elements of its progress in retrieving the output data
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。输出数据量大于输入数据量，并且输入数据量与输出数据量的比率定义了解压比。在一个实现中，由主机元件执行的与主机相关的高级别任务涉及高级图形处理任务，并且数据生成任务涉及生成几何数据（例如三角形顶点），用于在高级图形处理任务。 CPU模块可以经由至少一个锁定的高速缓存存储器将输出数据传送到GPU模块。 GPU从锁定的集合中检索输出数据，并周期性地将尾部指针转发到数据生成元素内的可缓存位置，以向数据生成元素通知其在检索输出数据中的进度

6. 发明申请

US20060098022A1 System and method for transfer of data between processors using a locked set, head and tail pointers 失效
标题翻译：使用锁定集，头和尾指针在处理器之间传输数据的系统和方法
公开(公告)号：US20060098022A1
公开(公告)日：2006-05-11
申请号：US11303525
申请日：2005-12-16
申请人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Russell Hoover , Eric Mejdrich , Sandra Woodward
发明人： Jeffrey Andrews , Nicholas Baker , J. Goossen , Russell Hoover , Eric Mejdrich , Sandra Woodward
IPC分类号： G09G5/36
CPC分类号： G06T15/005
摘要： A CPU module includes a host element configured to perform a high-level host-related task, and one or more data-generating processing elements configured to perform a data-generating task associated with the high-level host-related task. Each data-generating processing element includes logic configured to receive input data, and logic configured to process the input data to produce output data.
摘要翻译： CPU模块包括被配置为执行高级主机相关任务的主机元件，以及被配置为执行与高级主机相关任务相关联的数据生成任务的一个或多个数据生成处理元件。每个数据生成处理元件包括被配置为接收输入数据的逻辑和被配置为处理输入数据以产生输出数据的逻辑。

7. 发明申请

US20060080398A1 Direct access of cache lock set data without backing memory 失效
标题翻译：直接访问缓存锁集数据而无需备份内存
公开(公告)号：US20060080398A1
公开(公告)日：2006-04-13
申请号：US10961752
申请日：2004-10-08
申请人： Russell Hoover , Eric Mejdrich , Sandra Woodward
发明人： Russell Hoover , Eric Mejdrich , Sandra Woodward
IPC分类号： G06F15/167 , G06F12/00
CPC分类号： G06F12/126 , G06F12/084 , G06F2212/2515
摘要： Methods, apparatus, and systems for quickly accessing data residing in a cache of one processor, by another processor, while avoiding lengthy accesses to main memory are provided. A portion of the cache may be placed in a lock set mode by the processor in which it resides. While in the lock set mode, this portion of the cache may be accessed directly by another processor without lengthy “backing” writes of the accessed data to main memory.
摘要翻译：提供了用于快速访问驻留在一个处理器的高速缓存中的另一处理器的方法，装置和系统，同时避免对主存储器的长时间访问。高速缓存的一部分可以由其驻留的处理器置于锁定模式中。在锁定模式下，高速缓存的这一部分可能被另一个处理器直接访问，而不会对所访问的数据进行长时间的“后退”写入主存储器。

8. 发明申请

US20060080512A1 Graphics processor with snoop filter 失效
标题翻译：带窥探过滤器的图形处理器
公开(公告)号：US20060080512A1
公开(公告)日：2006-04-13
申请号：US10961750
申请日：2004-10-08
申请人： Russell Hoover , Eric Mejdrich
发明人： Russell Hoover , Eric Mejdrich
IPC分类号： G06F12/00
CPC分类号： G06F12/0831
摘要： Methods and apparatus that may be utilized to maintain coherency of data accessed by both a processor and a remote device are provided. The remote device may include coherency logic, referred to herein as a snoop filter, designed to filter memory access requests that do not require bus commands to be sent to the processor. The snoop filter may filter requests based on a remote cache directory designed to mirror the processor cache directory, such that only those requests that target cache lines indicated to be valid in the processor cache result in snoop commands sent to the processor. Other requests (targeting data that is not cached in the processor) may be routed directly to memory without the latency conventionally associated with snoop requests.
摘要翻译：提供了可用于维护由处理器和远程设备访问的数据的一致性的方法和装置。远程设备可以包括相关性逻辑，这里称为窥探过滤器，被设计为过滤不需要将总线命令发送到处理器的存储器访问请求。窥探过滤器可以基于旨在镜像处理器高速缓存目录的远程高速缓存目录来过滤请求，使得仅指示在处理器高速缓存中指示为有效的缓存行的那些请求导致发送到处理器的窥探命令。其他请求（目标数据不被缓存在处理器中）可以直接路由到存储器，而不需要通常与侦听请求相关联的延迟。

9. 发明申请

US20060015753A1 Internal RAM for integrity check values 审中-公开
标题翻译：内部RAM用于完整性检查值
公开(公告)号：US20060015753A1
公开(公告)日：2006-01-19
申请号：US10892430
申请日：2004-07-15
申请人： Robert Drehmel , William Hall , Russell Hoover
发明人： Robert Drehmel , William Hall , Russell Hoover
IPC分类号： G06F12/14 , H04L9/32 , G06F11/30
CPC分类号： G06F21/72 , H04L9/32
摘要： Methods and apparatus that may be utilized to reduce the amount of data related to encryption (hereinafter security metadata) that is accessible external to a device implementing the encryption, such as a system on a chip (SOC), are provided. The security metadata may be stored internal, for example in a secure random access memory (RAM) internal to the device, that is not accessible via external pins.
摘要翻译：提供了可以用于减少与实现加密的设备外部可访问的加密有关的数据量（以下称为安全元数据）的方法和装置，例如芯片上的系统（SOC）。安全元数据可以存储在内部，例如在设备内部的安全随机存取存储器（RAM）中，不能通过外部引脚访问。

10. 发明申请

US20050020516A1 Effects of combined administration of farnesyl transferase inhibitors and signal transduction inhibitors 审中-公开
标题翻译：联合施用法呢基转移酶抑制剂和信号转导抑制剂的作用
公开(公告)号：US20050020516A1
公开(公告)日：2005-01-27
申请号：US10870403
申请日：2004-06-17
申请人： George Daley , Russell Hoover
发明人： George Daley , Russell Hoover
IPC分类号： A61K31/473 , A61K31/495 , A61K45/06 , A61P35/02 , A61K31/704 , A61K31/33
CPC分类号： A61K45/06 , A61K31/473 , A61K31/495 , A61K31/435 , A61K2300/00
摘要： The present invention relates to methods of reducing proliferation of cells, enhancing apoptosis of cells or both in an individual in need thereof, comprising administering to the individual a combination of at least one farnesyl transferase inhibitor (FTI), such as an inhibitor of Ras function, and at least one signal transduction inhibitor (STI) in a therapeutically effective amount, wherein proliferation of cells is reduced and/or apoptosis of cells is enhanced in the individual. In one embodiment, the invention relates to a method of reducing proliferation of STI resistant cells, enhancing apoptosis of STI resistant cells, or both in an individual in need thereof, comprising administering to the individual a combination of at least one FTI and at least one STI in a therapeutically effective amount, wherein proliferation of STI resistant cells is reduced and/or apoptosis of STI resistant cells is enhanced in the individual. The present invention can be used to treat leukemia (e.g., CML) in an individual comprising administering to the individual a combination of at least one FTI and at least one STI in a therapeutically effective amount.
摘要翻译：本发明涉及在有需要的个体中减少细胞增殖，增强细胞凋亡或两者的方法，包括向个体施用至少一种法呢基转移酶抑制剂（FTI）的组合，例如Ras功能抑制剂，以及治疗有效量的至少一种信号转导抑制剂（STI），其中细胞的增殖被减少和/或细胞凋亡在个体中增强。在一个实施方案中，本发明涉及减少STI耐药细胞的增殖，增强STI耐药细胞的凋亡或在有需要的个体中二者的方法，包括向所述个体施用至少一种FTI和至少一种FTI的组合 STI在治疗有效量中，其中STI耐药细胞的增殖减少，和/或STI抗性细胞的细胞凋亡在个体中增强。本发明可用于治疗个体中的白血病（例如CML），其包括向个体施用治疗有效量的至少一种FTI和至少一种STI的组合。

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