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1. 发明申请

US20080237675A1 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US20080237675A1
公开(公告)日：2008-10-02
申请号：US11731543
申请日：2007-03-29
申请人： Brian S. Doyle , Roberts S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Roberts S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L27/108 , H01L21/20 , H01L29/92
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

2. 发明授权

US08138042B2 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US08138042B2
公开(公告)日：2012-03-20
申请号：US12967238
申请日：2010-12-14
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L27/108
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

3. 发明申请

US20110079837A1 CAPACITOR, METHOD OF INCREASING A CAPACITANCE AREA OF SAME, AND SYSTEM CONTAINING SAME 有权
标题翻译：电容器，增加其电容区域的方法和包含该电容器的系统
公开(公告)号：US20110079837A1
公开(公告)日：2011-04-07
申请号：US12967238
申请日：2010-12-14
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L27/108 , H01L21/8242
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

4. 发明授权

US07859081B2 Capacitor, method of increasing a capacitance area of same, and system containing same 有权
标题翻译：电容器，增加电容面积相同的方法，以及包含其的系统
公开(公告)号：US07859081B2
公开(公告)日：2010-12-28
申请号：US11731543
申请日：2007-03-29
申请人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Suman Datta , Vivek De , Ali Keshavarzi , Dinesh Somasekhar
IPC分类号： H01L29/92
CPC分类号： H01L28/91 , H01L27/10852 , H01L29/785
摘要： A capacitor includes a substrate (110, 210), a first electrically insulating layer (120, 220) over the substrate, and a fin (130, 231) including a semiconducting material (135) over the first electrically insulating layer. A first electrically conducting layer (140, 810) is located over the first electrically insulating layer and adjacent to the fin. A second electrically insulating layer (150, 910) is located adjacent to the first electrically conducting layer, and a second electrically conducting layer (160, 1010) is located adjacent to the second electrically insulating layer. The first and second electrically conducting layers together with the second electrically insulating layer form a metal-insulator-metal stack that greatly increases the capacitance area of the capacitor. In one embodiment the capacitor is formed using what may be referred to as a removable metal gate (RMG) approach.
摘要翻译：电容器包括衬底（110,210），在衬底上方的第一电绝缘层（120,220）以及在第一电绝缘层上包括半导体材料（135）的翅片（130,231）。第一导电层（140,810）位于第一电绝缘层上并且邻近鳍片。第二电绝缘层（150,910）位于第一导电层附近，并且第二导电层（160,1010）位于第二电绝缘层附近。第一和第二导电层与第二电绝缘层一起形成金属 - 绝缘体 - 金属叠层，其大大增加了电容器的电容面积。在一个实施例中，使用可被称为可拆卸金属门（RMG）方法形成电容器。

5. 发明申请

US20080237678A1 On-chip memory cell and method of manufacturing same 审中-公开
标题翻译：片上存储单元及其制造方法
公开(公告)号：US20080237678A1
公开(公告)日：2008-10-02
申请号：US11729192
申请日：2007-03-27
申请人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
发明人： Suman Datta , Jack T. Kavalieros , Brian S. Doyle , Dinesh Somasekhar , Ali Keshavarzi
IPC分类号： H01L27/108 , H01L21/336
CPC分类号： H01L27/10873 , H01L27/10826 , H01L29/785
摘要： An on-chip memory cell comprises a tri-gate access transistor (145) and a tri-gate capacitor (155). The on-chip memory cell may be an embedded DRAM on a three-dimensional tri-gate transistor and capacitor structures which is fully compatible with existing tri-gate logic transistor fabrication process. Embodiments of the invention use the high fin aspect ratio and inherently superior surface area of the tri-gate transistors to replace the “trench” capacitor in a commodity DRAM with an inversion mode tri-gate capacitor. The tall sidewalls of the tri-gate transistor provide large enough surface area to provide storage capacitance in a small cell area.
摘要翻译：片上存储单元包括三栅极存取晶体管（145）和三栅极电容器（155）。片上存储器单元可以是三维三栅晶体管上的嵌入式DRAM和与现有三栅逻辑晶体管制造工艺完全兼容的电容器结构。本发明的实施例使用三栅极晶体管的高翅片长宽比和固有优越的表面积来替代具有反向模式三栅极电容器的商品DRAM中的“沟槽”电容器。三栅极晶体管的高侧壁提供足够大的表面积，以在小单元区域中提供存储电容。

6. 发明申请

US20060014331A1 Floating-body DRAM in tri-gate technology 有权
标题翻译：三门技术中的浮体DRAM
公开(公告)号：US20060014331A1
公开(公告)日：2006-01-19
申请号：US10879480
申请日：2004-06-30
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L21/84
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.
摘要翻译：浮体动态随机存取存储器件可以包括半导体本体，其具有形成在衬底上的顶表面和横向相对的侧壁。可以在半导体主体的顶表面和半导体本体的横向相对的侧壁上形成栅介质层。栅极电极可以形成在半导体本体的顶表面上的栅极电介质上并与半导体本体的横向相对的侧壁上的栅电介质相邻。栅电极可能仅部分地耗尽半导体本体的区域，并且部分耗尽的区域可以用作逻辑状态的存储节点。

7. 发明申请

US20060267093A1 Floating-body dynamic random access memory and method of fabrication in tri-gate technology 有权
公开(公告)号：US20060267093A1
公开(公告)日：2006-11-30
申请号：US11429490
申请日：2006-05-04
申请人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
发明人： Stephen Tang , Ali Keshavarzi , Dinesh Somasekhar , Fabrice Paillet , Muhammad Khellah , Yibin Ye , Shih-Lien Lu , Brian Doyle , Suman Datta , Vivek De
IPC分类号： H01L27/12
CPC分类号： H01L29/785 , H01L27/108 , H01L27/10802 , H01L27/10826 , H01L27/10876 , H01L27/10879 , H01L29/66795 , H01L29/7841
摘要： A floating-body dynamic random access memory device may include a semiconductor body having a top surface and laterally opposite sidewalls formed on a substrate. A gate dielectric layer may be formed on the top surface of the semiconductor body and on the laterally opposite sidewalls of the semiconductor body. A gate electrode may be formed on the gate dielectric on the top surface of the semiconductor body and adjacent to the gate dielectric on the laterally opposite sidewalls of the semiconductor body. The gate electrode may only partially deplete a region of the semiconductor body, and the partially depleted region may be used as a storage node for logic states.

8. 发明授权

US08232588B2 Increasing the surface area of a memory cell capacitor 有权
标题翻译：增加存储单元电容器的表面积
公开(公告)号：US08232588B2
公开(公告)日：2012-07-31
申请号：US12749389
申请日：2010-03-29
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L27/108 , H01L29/94
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。在第三绝缘层上沉积第二导电层。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

9. 发明申请

US20100181607A1 INCREASING THE SURFACE AREA OF A MEMORY CELL CAPACITOR 有权
标题翻译：增加记忆体电容器的表面积
公开(公告)号：US20100181607A1
公开(公告)日：2010-07-22
申请号：US12749389
申请日：2010-03-29
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L27/06
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。第二导电层沉积在第三绝缘层上。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

10. 发明申请

US20080237796A1 Increasing the surface area of a memory cell capacitor 有权
标题翻译：增加存储单元电容器的表面积
公开(公告)号：US20080237796A1
公开(公告)日：2008-10-02
申请号：US11731193
申请日：2007-03-30
申请人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
发明人： Brian S. Doyle , Robert S. Chau , Vivek De , Suman Datta , Dinesh Somasekhar
IPC分类号： H01L29/92 , H01L21/20
CPC分类号： H01L28/91 , H01L27/10817 , H01L27/10852
摘要： Methods and apparatuses to increase a surface area of a memory cell capacitor are described. An opening in a second insulating layer deposited over a first insulating layer on a substrate is formed. The substrate has a fin. A first insulating layer is deposited over the substrate adjacent to the fin. The opening in the second insulating layer is formed over the fin. A first conducting layer is deposited over the second insulating layer and the fin. A third insulating layer is deposited on the first conducting layer. A second conducting layer is deposited on the third insulating layer. The second conducting layer fills the opening. The second conducting layer is to provide an interconnect to an upper metal layer. Portions of the second conducting layer, third insulating layer, and the first conducting layer are removed from a top surface of the second insulating layer.
摘要翻译：描述了增加存储单元电容器的表面积的方法和装置。形成了沉积在基板上的第一绝缘层上的第二绝缘层中的开口。衬底具有翅片。第一绝缘层沉积在邻近鳍片的衬底上。第二绝缘层上的开口形成在鳍上。第一导电层沉积在第二绝缘层和鳍上。第三绝缘层沉积在第一导电层上。在第三绝缘层上沉积第二导电层。第二导电层填充开口。第二导电层是提供与上金属层的互连。从第二绝缘层的顶表面去除第二导电层，第三绝缘层和第一导电层的部分。

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