会员体验
专利管家(专利管理)
工作空间(专利管理)
风险监控(情报监控)
数据分析(专利分析)
侵权分析(诉讼无效)
联系我们
交流群
官方交流:
QQ群: 891211   
微信请扫码    >>>
现在联系顾问~
热词
    • 6. 发明授权
    • Touch history table
    • 触摸历史记录表
    • US6055621A
    • 2000-04-25
    • US599833
    • 1996-02-12
    • Thomas Roberts Puzak
    • Thomas Roberts Puzak
    • G06F9/38
    • G06F9/3802G06F9/30047G06F9/3455G06F9/383G06F9/3832G06F9/3844
    • A mechanism is described that predicts the success or failure of prefetching instructions based on the previous performance of the instructions. A prefetching instruction is successful if the block of information prefetched into the cache is used by the processor before it is discarded from the cache. A prefetching instruction is unsuccessful, a failure, if the block of information prefetched into the cache is not used while in the cache. The prediction regarding the success or failure of the prefetching instruction is performed utilizing a table that records the history regarding the usefulness of each prefetch made by a prefetching instruction at a given memory location. The table is called a Touch-History-Table (THT). The THT is preferably accessed during the decode phase of each instruction using the memory location of the instruction. The table records the history of previous outcomes (success or failure) of the prefetching instruction up to the table size. If a prefetch instruction is predicted as successful then a prefetch will occur and if a prefetch instruction is predicted as unsuccessful then no prefetch will be attempted.
    • 描述了一种基于先前执行指令来预测预取指令的成功或失败的机制。 如果预取到高速缓存中的信息块在从缓存中丢弃之前被处理器使用,则预取指令是成功的。 如果在高速缓存中不使用预取到高速缓存中的信息块,则预取指令不成功,故障。 关于预取指令的成功或失败的预测是利用记录关于由预取指令在给定存储器位置进行的每个预取的有用性的历史的表执行的。 该表称为触摸历史表(THT)。 优选地,在使用指令的存储器位置的每个指令的解码阶段期间访问THT。 该表将预取指令的以前结果(成功或失败)的历史记录记录到表格大小。 如果预取指令被预测成功,则将发生预取,并且如果预取指令被预测为不成功,则不尝试预取。
    • 7. 发明授权
    • Operand prefetch table
    • 操作数预取表
    • US5790823A
    • 1998-08-04
    • US502115
    • 1995-07-13
    • Thomas Roberts PuzakHarold Stuart Stone
    • Thomas Roberts PuzakHarold Stuart Stone
    • G06F9/38G06F12/08G06F9/30
    • G06F9/383G06F12/0862G06F9/3455
    • A operand prefetching mechanism is described for a system having a cache, in addition to its normal memory. The prefetch apparatus utilizes a table that records the location of each instruction that caused an operand miss and the location of the miss. Associated with this information is the address of each instruction fetch block that contains an instruction that caused an operand miss. The table is called an Operand Prefetch Table. With each instruction block fetched from the cache a search is made of the Operand Prefetch table to determine if the instructions found in this block previously caused operand misses. If the instruction block fetched matches an entry in the Operand Prefetch Table then a prefetch for future operands can be attempted for the instructions contained within the instruction block fetch segment.
    • 对于具有高速缓存的系统,除了其正常存储器之外,还描述了操作数预取机制。 预取装置利用记录导致操作数丢失的指令的位置和未命中的位置的表。 与该信息相关联的是每个指令获取块的地址,该地址包含导致操作数丢失的指令。 该表称为操作数预取表。 对于从缓存中取出的每个指令块,搜索操作数预取表,以确定此块中发现的指令是否先前导致操作数丢失。 如果读取的指令块与操作数预取表中的条目匹配,则可以针对指令块提取段中包含的指令尝试将来的操作数的预取。