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1. 发明授权

US06996737B2 System and method for delayed increment of a counter 失效
标题翻译：计数器延迟增量的系统和方法
公开(公告)号：US06996737B2
公开(公告)日：2006-02-07
申请号：US10680521
申请日：2003-10-07
申请人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
发明人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
IPC分类号： G06F1/04
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
摘要翻译：提供了用于执行延迟计数器增量的方法和结构。该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。因此，计数器递增指令被改变。延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

2. 发明授权

US06658584B1 Method and structure for managing large counter arrays 有权
标题翻译：管理大型计数器阵列的方法和结构
公开(公告)号：US06658584B1
公开(公告)日：2003-12-02
申请号：US09656556
申请日：2000-09-06
申请人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
发明人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
IPC分类号： G06F104
CPC分类号： G06F1/04
摘要： A method and structure for counting and storing the number of occurrences of each of a plurality of events occurring in a processor complex, which processor complex has at least one processor which processes multiple groups of data in a multiplicity of ways, is provided. The structure includes multiple storage devices, each of which includes a plurality of arrays of memory storage for storing count information of each event, which arrays are divided into a plurality of separately addressable groups of memory addresses in each memory array. At least one counter element is associated with each array of memory. A table is provided which contains information, including a point of reference in each array to uniquely define the structure and location of each memory array. At least one processor generates a plurality of parameters for each of the events to uniquely identify the event. A counter manager is provided which communicates with said at least one processor through its associated coprocessors and receives the parameters of each event generated from the at least one processor. The counter manager, utilizing the table and the parameters information from the at least one processor determines the unique physical address location associated with the event, reads the data from the unique address, modifies the read data according to the instructions and writes the modified data to the determined address. The invention also contemplates reading the information which has been stored for statistical evaluation at the address without modifying the stored information.
摘要翻译：提供了一种用于计数和存储在处理器复合体中发生的多个事件中的每一个的出现次数的方法和结构，该处理器复合体具有以多种方式处理多组数据的至少一个处理器。该结构包括多个存储设备，每个存储设备包括用于存储每个事件的计数信息的多个存储器存储阵列，哪些阵列被划分成每个存储器阵列中的多个单独可寻址的存储器地址组。至少一个计数器元件与每个存储器阵列相关联。提供了一个包含信息的表，其中包括每个数组中的参考点，以唯一地定义每个存储器阵列的结构和位置。至少一个处理器为每个事件生成多个参数以唯一地识别该事件。提供了一种计数器管理器，其经由其相关联的协处理器与所述至少一个处理器进行通信，并接收从至少一个处理器生成的每个事件的参数。计数器管理器利用来自至少一个处理器的表和参数信息确定与事件相关联的唯一物理地址位置，从唯一地址读取数据，根据指令修改读取的数据，并将修改的数据写入确定的地址。本发明还考虑在不修改存储的信息的情况下读取已经存储的用于统计评估的地址的信息。

3. 发明授权

US06701447B1 System for delaying the counting of occurrences of a plurality of events occurring in a processor until the disposition of the event has been determined 失效
标题翻译：用于延迟在处理器中发生的多个事件的发生的计数的系统，直到已经确定了事件的处理
公开(公告)号：US06701447B1
公开(公告)日：2004-03-02
申请号：US09656547
申请日：2000-09-06
申请人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
发明人： Brian Mitchell Bass , Gordon Taylor Davis , Marco C. Heddes
IPC分类号： G06F104
CPC分类号： G06F11/3466 , G06F2201/86 , G06F2201/88
摘要： A method and structure for performing a delayed counter increment is provided. The method and structure allows a counter decision to be modified based upon what the computer system hardware does with the data packet. Subsequent to the generation of a counter command, the processing of the data packet may change: for example, the data packet may be discarded instead of forwarded. Accordingly, the counter increment instruction is changed. A delayed counter increment will perform the actual counter update after the processing of the data packet is completed. In one embodiment of the invention, the counter update action is modified depending upon whether the data packet is forwarded or discarded, and a different counter is selected to be updated. This solves a problem that sometimes the forwarding code is unable to determine if some independent action may later discard a data packet.
摘要翻译：提供了用于执行延迟计数器增量的方法和结构。该方法和结构允许基于计算机系统硬件对数据分组进行什么来修改计数器判定。在产生计数器命令之后，数据分组的处理可能改变：例如，数据分组可以被丢弃而不是转发。因此，计数器递增指令被改变。延迟计数器增量将在数据包的处理完成后执行实际的计数器更新。在本发明的一个实施例中，根据数据分组是转发还是丢弃，并且选择不同的计数器来更新计数器更新动作。这解决了有时转发代码无法确定某些独立操作是否可能稍后丢弃数据包的问题。

4. 发明授权

US07139753B2 Full match (FM) search algorithm implementation for a network processor 失效
标题翻译：网络处理器的完全匹配（FM）搜索算法实现
公开(公告)号：US07139753B2
公开(公告)日：2006-11-21
申请号：US10650327
申请日：2003-08-28
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Antonios Maragkos , Piyush Chunilal Patel , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F7/00 , H04L12/28
CPC分类号： H04L45/742 , H04L45/7453 , Y10S707/99933 , Y10S707/99934 , Y10S707/99935 , Y10S707/99936 , Y10S707/99937 , Y10S707/99943 , Y10S707/99945
摘要： Novel data structures, methods and apparatus for finding a full match between a search pattern and a pattern stored in a leaf of the search tree. A key is input, a hash function is performed on the key, a direct table (DT) is accessed, and a tree is walked through pattern search control blocks (PSCBs) until reaching a leaf. The search mechanism uses a set of data structures that can be located in a few registers and regular memory, and then used to build a Patricia tree structure that can be manipulated by a relatively simple hardware macro. Both keys and corresponding information needed for retrieval are stored in the Patricia tree structure. The hash function provides an n->n mapping of the bits of the key to the bits of the hash key. The data structure that is used to store the hash key and the related information in the tree is called a leaf. Each leaf corresponds to a single key that matches exactly with the input key. The leaf contains the key as well as additional information. The length of the leaf is programmable, as is the length of the key. The leaf is stored in random access memory and is implemented as a single memory entry. If the key is located in the direct table then it is called a direct leaf.
摘要翻译：用于在搜索图案和存储在搜索树的叶中的模式之间找到完全匹配的新型数据结构，方法和装置。键输入，对密钥执行哈希函数，访问直接表（DT），并通过模式搜索控制块（PSCB），树直到达到叶。搜索机制使用一组可以位于几个寄存器和常规内存中的数据结构，然后用于构建可由相对简单的硬件宏操作的Patricia树结构。检索所需的两个密钥和相应的信息都存储在Patricia树结构中。散列函数提供密钥的比特到散列密钥的比特的n> n映射。用于存储散列键和树中相关信息的数据结构称为叶。每个叶对应于与输入键完全匹配的单个键。叶包含关键以及其他信息。叶片的长度是可编程的，密钥的长度也是可编程的。叶存储在随机存取存储器中，并被实现为单个存储器条目。如果键位于直接表中，则称为直接叶。

5. 发明授权

US07106730B1 Method and apparatus for processing frame classification information between network processors 失效
标题翻译：用于处理网络处理器之间帧分类信息的方法和装置
公开(公告)号：US07106730B1
公开(公告)日：2006-09-12
申请号：US09546833
申请日：2000-04-11
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/30
摘要： A network device including an ingress processor and egress processor which receives frames of data over the network on an input port, and transfers it to an appropriate output port. The received frame is processed by an ingress processor which prepares an intra-switch frame for delivery to an egress processor serving a relevant output port of the switch. The intra-switch frame includes a frame header having parameters which have been determined by the ingress processor, as well as data indicating an address for the egress processor for beginning processing of the frame. By identifying to the egress processor processing which has already taken place, the egress processor is relieved of any redundant processing of the frame. The egress processor provides a hardware frame classifier which decodes the information contained in the intra-frame header to derive parameters which have been previously computed as well as a starting address for the egress processor. By reducing the amount of redundant processing of the egress processor, total device throughput delay is reduced.
摘要翻译：一种网络设备，包括入口处理器和出口处理器，其在输入端口上通过网络接收数据帧，并将其传送到适当的输出端口。接收到的帧由入口处理器处理，入口处理器准备一个内部交换帧，用于传送到服务于交换机的相关输出端口的出口处理器。帧内切换帧包括具有由入口处理器确定的参数的帧报头，以及指示用于开始处理该帧的出口处理器的地址的数据。通过识别已经发生的出口处理器处理，出口处理器免除了帧的任何冗余处理。出口处理器提供硬件帧分类器，其对包含在帧内报头中的信息进行解码以导出先前已经计算的参数以及出口处理器的起始地址。通过减少出口处理器的冗余处理量，减少了总设备吞吐量延迟。

6. 发明授权

US06862292B1 Method and system for network processor scheduling outputs based on multiple calendars 失效
标题翻译：基于多个日历的网络处理器调度输出的方法和系统
公开(公告)号：US06862292B1
公开(公告)日：2005-03-01
申请号：US09548910
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： H04L12/56 , H04Q11/04 , H04L12/28
CPC分类号： H04Q11/0478 , H04L47/2425 , H04L47/50 , H04L47/52 , H04L47/627 , H04L2012/5636 , H04L2012/5649 , H04L2012/5651 , H04L2012/5679 , H04L2012/5681
摘要： A system and method of moving information units from a network processor toward a data transmission network in a prioritized sequence which accommodates several different levels of service. The present invention includes a method and system for scheduling the egress of processed information units (or frames) from a network processing unit according to stored priorities associated with the various sources of the information units. The priorities in the preferred embodiment include a low latency service, a minimum bandwidth, a weighted fair queueing and a system for preventing a user from continuing to exceed his service levels over an extended period. The present invention includes a plurality of calendars with different service rates to allow a user to select the service rate which he desires. If a customer has chosen a high bandwidth for service, the customer will be included in a calendar which is serviced more often than if the customer has chosen a lower bandwidth.
摘要翻译：一种将信息单元从网络处理器移动到数据传输网络的系统和方法，其以容纳几个不同级别的服务的优先顺序排列。本发明包括一种方法和系统，用于根据存储的与信息单元的各种源相关联的优先级来调度来自网络处理单元的处理的信息单元（或帧）的出口。优选实施例中的优先级包括低延迟服务，最小带宽，加权公平排队以及用于在较长时间内防止用户继续超过其服务水平的系统。本发明包括具有不同服务速率的多个日历，以允许用户选择他所期望的服务速率。如果客户选择了高带宽的服务，客户将被包含在比客户选择较低带宽的情况下更频繁地服务的日历。

7. 发明授权

US06795870B1 Method and system for network processor scheduler 失效
标题翻译：网络处理器调度程序的方法和系统
公开(公告)号：US06795870B1
公开(公告)日：2004-09-21
申请号：US09548907
申请日：2000-04-13
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Marco C. Heddes , Michael Steven Siegel , Fabrice Jean Verplanken
IPC分类号： G06F300
CPC分类号： H04L47/568 , H04L47/50
摘要： A system and method uses grouped calendars, flow queues, pointers and stored rules to process information packets so that different flow control characteristics associated with the information units are maintained.
摘要翻译：系统和方法使用分组的日历，流队列，指针和存储的规则来处理信息分组，从而保持与信息单元相关联的不同流控制特性。

8. 发明授权

US07620048B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07620048B2
公开(公告)日：2009-11-17
申请号：US11152419
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： An apparatus is disclosed for transporting control information in a communications system. The apparatus comprises a network processor, a control point processor operatively coupled to the network processor, and a guided frame generated by the control point processor. The guided frame comprises a first section in which frame control information is placed and is used by the network processor to update at least one control register within the network processor; a second section carrying correlators assigned by the control point processor to correlate guided frame responses with their requests; a third section carrying one or a sequence of guided commands; and an End delimiter guided command.
摘要翻译：公开了用于在通信系统中传送控制信息的装置。该装置包括网络处理器，可操作地耦合到网络处理器的控制点处理器以及由控制点处理器生成的引导帧。引导帧包括其中放置帧控制信息的第一部分，并且被网络处理器用于更新网络处理器内的至少一个控制寄存器; 第二部分，承载由控制点处理器分配的相关器，以将引导的帧响应与其请求相关联; 第三部分承载一个或一系列指导命令; 和一个结束分隔符引导命令。

9. 发明授权

US07590057B2 Network switch and components and method of operation 有权
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07590057B2
公开(公告)日：2009-09-15
申请号：US11152453
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/26 , H04L12/66 , G06F15/16
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A control sub system, a plurality of interface processors, a plurality of media interfaces a plurality of queues are operatively coupled and responsive to a control signal to move data from a memory to a selected one of the plurality of queues.
摘要翻译：控制子系统，多个接口处理器，多个媒体接口，多个队列可操作地耦合并且响应于控制信号将数据从存储器移动到多个队列中的所选择的一个队列。

10. 发明授权

US07257616B2 Network switch and components and method of operation 失效
标题翻译：网络交换机及组件及操作方法
公开(公告)号：US07257616B2
公开(公告)日：2007-08-14
申请号：US11152119
申请日：2005-06-14
申请人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
发明人： Brian Mitchell Bass , Jean Louis Calvignac , Anthony Matteo Gallo , Marco C. Heddes , Sridhar Rao , Michael Steven Siegel , Brian Alan Youngman , Fabrice Jean Verplanken
IPC分类号： H04L12/28
CPC分类号： H04L49/3036 , G06F13/4022 , H04L49/15 , H04L49/205 , H04L49/3009 , H04L49/351
摘要： A network switch apparatus, components for such an apparatus, and methods of operating such an apparatus in which data flow handling and flexibility is enhanced by the cooperation of a control point and a plurality of interface processors formed on a semiconductor substrate. The control point and interface processors together form a network processor capable of cooperating with other elements including an optional switching fabric device in executing instructions directing the flow of data in a network.
摘要翻译：一种网络交换装置，这种装置的组件，以及操作这样的装置的方法，其中通过控制点和形成在半导体衬底上的多个接口处理器的协作来增强数据流处理和灵活性。控制点和接口处理器一起形成一个网络处理器，能够在执行指导网络中的数据流的指令的情况下与包括可选交换结构设备在内的其他元件协作。

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