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    • 1. 发明授权
    • Post high-k dielectric/metal gate clean
    • 后高k电介质/金属门清洁
    • US07732284B1
    • 2010-06-08
    • US12344421
    • 2008-12-26
    • Brian K. KirkpatrickJinhan ChoiDeborah J. Riley
    • Brian K. KirkpatrickJinhan ChoiDeborah J. Riley
    • H01L21/00
    • H01L21/02071H01L21/31111H01L29/517H01L29/78Y10S438/906
    • A method for fabricating a CMOS integrated circuit (IC) includes the step of providing a substrate having a semiconductor surface. A gate stack including a metal gate electrode on a metal including high-k dielectric layer is formed on the semiconductor surface. Dry etching is used to pattern the gate stack to define a patterned gate electrode stack having exposed sidewalls of the metal gate electrode. The dry etching forms post etch residuals some of which are deposited on the substrate. The substrate including the patterned gate electrode stack is exposed to a solution cleaning sequence including a first clean step including a first acid and a fluoride for removing at least a portion of the post etch residuals, wherein the first clean step has a high selectivity to avoid etching the exposed sidewalls of the metal gate electrode. A second clean after the first clean consists essentially of a fluoride which removes residual high-k material on the semiconductor surface.
    • 制造CMOS集成电路(IC)的方法包括提供具有半导体表面的衬底的步骤。 在半导体表面上形成包括金属栅电极在包含高k电介质层的金属上的栅叠层。 使用干蚀刻来图案化栅极堆叠以限定具有金属栅电极的暴露侧壁的图案化栅电极堆叠。 干蚀刻形成后蚀刻残留物,其中一些沉积在基底上。 包括图案化的栅极电极堆叠的衬底暴露于溶液清洁序列,其包括包括第一酸和氟化物的第一清洁步骤,用于去除至少一部分后蚀刻残留物,其中第一清洁步骤具有高选择性以避免 蚀刻金属栅电极的暴露的侧壁。 第一次清洁后的第二次清洁基本上由氟化物组成,其除去半导体表面上残留的高k材料。
    • 2. 发明申请
    • NITRIDE REMOVAL WHILE PROTECTING SEMICONDUCTOR SURFACES FOR FORMING SHALLOW JUNCTIONS
    • 保护半导体表面的氮化物去除形成微结点
    • US20100248440A1
    • 2010-09-30
    • US12731913
    • 2010-03-25
    • Brian K. KirkpatrickDeborah J. Riley
    • Brian K. KirkpatrickDeborah J. Riley
    • H01L21/336
    • H01L21/2652H01L29/6653H01L29/6656
    • A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
    • 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成,其一起限定轻掺杂漏极(LDD)区域或源极/漏极(S / D)区域。 侧壁间隔物,LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除,其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层,或者当LDD或S / D区域包括 暴露的氮化硅层,在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。
    • 3. 发明授权
    • Nitride removal while protecting semiconductor surfaces for forming shallow junctions
    • 氮化物去除同时保护半导体表面以形成浅结
    • US08043921B2
    • 2011-10-25
    • US12731913
    • 2010-03-25
    • Brian K. KirkpatrickDeborah J. Riley
    • Brian K. KirkpatrickDeborah J. Riley
    • H01L21/336
    • H01L21/2652H01L29/6653H01L29/6656
    • A method of removing silicon nitride over a semiconductor surface for forming shallow junctions. Sidewall spacers are formed along sidewalls of a gate stack that together define lightly doped drain (LDD) regions or source/drain (S/D) regions. At least one of the sidewall spacers, LDD regions and S/D regions include an exposed silicon nitride layer. The LDD or S/D regions include a protective dielectric layer formed directly on the semiconductor surface. Ion implanting implants the LDD regions or S/D regions using the sidewall spacers as implant masks. The exposed silicon nitride layer is selectively removed, wherein the protective dielectric layer when the sidewall spacers include the exposed silicon nitride layer, or a replacement protective dielectric layer formed directly on the semiconductor surface after ion implanting when the LDD or S/D regions include the exposed silicon nitride layer, protects the LDD or S/D regions from dopant loss due to etching during selectively removing.
    • 一种在半导体表面上去除氮化硅以形成浅结的方法。 侧壁间隔物沿着栅堆叠的侧壁形成,其一起限定轻掺杂漏极(LDD)区域或源极/漏极(S / D)区域。 侧壁间隔物,LDD区域和S / D区域中的至少一个包括暴露的氮化硅层。 LDD或S / D区域包括直接形成在半导体表面上的保护电介质层。 离子注入使用侧壁间隔物作为植入物掩模来植入LDD区域或S / D区域。 暴露的氮化硅层被选择性地去除,其中当侧壁间隔物包括暴露的氮化硅层时的保护电介质层,或者当LDD或S / D区域包括 暴露的氮化硅层,在选择性去除期间由于蚀刻而保护LDD或S / D区域免受掺杂剂损失。
    • 7. 发明申请
    • METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE HAVING IMPROVED ACROSS CHIP IMPLANT UNIFORMITY
    • 制造具有改进的切片植入均匀性的半导体器件的方法
    • US20080153273A1
    • 2008-06-26
    • US11615187
    • 2006-12-22
    • Karen H.R. KirmseYuanning ChenJarvis B. JacobsDeborah J. Riley
    • Karen H.R. KirmseYuanning ChenJarvis B. JacobsDeborah J. Riley
    • H01L21/425
    • H01L21/823468H01L21/823418H01L21/823814H01L21/823864
    • The present invention provides a method for manufacturing a semiconductor device. The method for manufacturing the semiconductor device, in one embodiment, includes forming a gate structure over a substrate, and forming a stack of layers on the substrate and at least partially along a sidewall of the gate structure. In this embodiment, the stack of layers includes an initial layer located over the substrate, a buffer layer located over the initial layer and an offset layer located over the buffer layer. This embodiment of the method further includes removing horizontal segments of the offset layer and the buffer layer using a dry etch and a wet clean, wherein removing includes choosing at least one of an initial thickness of the buffer layer, a period of time for the dry etch or a period of time for the wet clean such that horizontal segments of the initial layer are exposed and substantially unaffected after the dry etch and wet clean.
    • 本发明提供一种制造半导体器件的方法。 在一个实施例中,用于制造半导体器件的方法包括在衬底上形成栅极结构,并且在衬底上并且至少部分地沿栅极结构的侧壁形成层叠层。 在该实施例中,层叠层包括位于衬底上的初始层,位于初始层之上的缓冲层和位于缓冲层上方的偏移层。 该方法的该实施例还包括使用干蚀刻和湿清洁来去除偏移层和缓冲层的水平段,其中移除包括选择缓冲层的初始厚度中的至少一个,干燥时间 蚀刻或湿式清洁的时间段,使得初始层的水平段在干蚀刻和湿清洁之后暴露并基本上不受影响。
    • 8. 发明授权
    • Strain-engineered MOSFETs having rimmed source-drain recesses
    • 具有边缘源极 - 漏极凹槽的应变工程MOSFET
    • US08877581B2
    • 2014-11-04
    • US12855736
    • 2010-08-13
    • Amitabh JainDeborah J. Riley
    • Amitabh JainDeborah J. Riley
    • H01L29/78H01L21/8238
    • H01L21/823814H01L21/823807H01L29/7848
    • An integrated circuit (IC) includes a plurality of strained metal oxide semiconductor (MOS) devices that include a semiconductor surface having a first doping type, a gate electrode stack over a portion of the semiconductor surface, and source/drain recesses that extend into the semiconductor surface and are framed by semiconductor surface interface regions on opposing sides of the gate stack. A first epitaxial strained alloy layer (rim) is on the semiconductor surface interface regions, and is doped with the first doping type. A second epitaxial strained alloy layer is on the rim and is doped with a second doping type that is opposite to the first doping type that is used to form source/drain regions.
    • 集成电路(IC)包括多个应变金属氧化物半导体(MOS)器件,其包括具有第一掺杂类型的半导体表面,半导体表面的一部分上的栅极电极堆叠以及延伸到 半导体表面并且由栅堆叠的相对侧上的半导体表面界面区域构成。 第一外延应变合金层(边缘)在半导体表面界面区域上,并掺杂有第一掺杂型。 第二外延应变合金层位于边缘上并且掺杂有与用于形成源极/漏极区的第一掺杂类型相反的第二掺杂类型。
    • 9. 发明申请
    • DIFFERENTIAL OFFSET SPACER
    • 差异偏移距离
    • US20090098695A1
    • 2009-04-16
    • US11870241
    • 2007-10-10
    • Shashank EkboteDeborah J. RileyBorna Obradovic
    • Shashank EkboteDeborah J. RileyBorna Obradovic
    • H01L21/8238H01L21/8244
    • H01L27/1104G11C11/412H01L21/823864H01L27/11
    • A method of fabricating a CMOS integrated circuit includes the steps of providing a substrate having a semiconductor surface, forming a gate dielectric and a plurality of gate electrodes thereon in both NMOS and PMOS regions using the surface. A multi-layer offset spacer stack including a top layer and a compositionally different bottom layer is formed and the multi-layer spacer stack is etched to form offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize a thinner offset spacer are covered with a first masking material, and transistors designed to utilize a thicker offset spacer are patterned and first implanted. At least a portion of the top layer is removed to leave the thinner offset spacers on sidewalls of the gate electrodes. The transistors designed to utilize the thicker offset spacer are covered with a second masking material, and the transistors designed to utilize the thinner offset spacer are patterned and second implanted. The fabrication of the integrated circuit is then completed.
    • 制造CMOS集成电路的方法包括以下步骤:使用该表面在NMOS和PMOS区域中提供具有半导体表面的衬底,在其上形成栅极电介质和多个栅电极。 形成包括顶层和组成不同底层的多层偏移间隔堆叠,并且蚀刻多层间隔堆叠以在栅电极的侧壁上形成偏置间隔物。 设计成利用较薄的偏移间隔物的晶体管被​​第一掩模材料覆盖,并且被设计成利用更厚的偏移间隔物的晶体管被​​图案化并且首先被注入。 去除顶层的至少一部分以在栅电极的侧壁上留下较薄的偏移间隔物。 设计成利用较厚的偏移间隔物的晶体管被​​第二掩模材料覆盖,并且设计成利用较薄的偏移间隔物的晶体管被​​图案化并且被第二次注入。 然后完成集成电路的制造。