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1. 发明授权

US09285865B2 Dynamic link scaling based on bandwidth utilization 有权
标题翻译：基于带宽利用率的动态链路缩放
公开(公告)号：US09285865B2
公开(公告)日：2016-03-15
申请号：US13539294
申请日：2012-06-29
申请人： Brian F. Keish , Thomas M. Wicki , Sebastian Turullols
发明人： Brian F. Keish , Thomas M. Wicki , Sebastian Turullols
IPC分类号： G06F1/00 , G06F1/32 , G06F13/38 , H04N21/231
CPC分类号： G06F1/3243 , G06F1/32 , G06F1/3203 , G06F1/3209 , G06F1/3253 , G06F1/3287 , G06F13/38 , H04N21/23106 , Y02D10/151 , Y02D10/152
摘要： Systems and methods for reducing power consumption during data transport across multiple processors when link utilization is low. In a multi-node system, at least one of two nodes may indicate low utilization for a given link between them. In response to further determining no enabled link between the two nodes is over utilized, each of the two nodes may remove the given link from consideration for being scheduled to receive data for transfer and turn off the given link when no more transactions are scheduled for the given link. Disabled links may be re-enabled when high utilization is detected on at least one link between the two nodes.
摘要翻译：当链路利用率低时，可以在多个处理器之间传输数据时降低功耗的系统和方法。在多节点系统中，两个节点中的至少一个可以指示它们之间给定链路的低利用率。响应于进一步确定两个节点之间没有启用的链路被过度利用，两个节点中的每一个节点可以将给定链路从考虑中去除以被调度以接收用于传送的数据，并且在没有为给定链接。当在两个节点之间的至少一个链路上检测到高利用率时，可以重新启用禁用链路。

2. 发明申请

US20140040526A1 COHERENT DATA FORWARDING WHEN LINK CONGESTION OCCURS IN A MULTI-NODE COHERENT SYSTEM 审中-公开
标题翻译：多节点相关系统中的链路聚合故障时的相关数据转发
公开(公告)号：US20140040526A1
公开(公告)日：2014-02-06
申请号：US13563586
申请日：2012-07-31
申请人： Bruce J. Chang , Sebastian Turullols , Brian F. Keish , Damien Walker , Ramaswamy Sivaramakrishnan , Paul N. Loewenstein
发明人： Bruce J. Chang , Sebastian Turullols , Brian F. Keish , Damien Walker , Ramaswamy Sivaramakrishnan , Paul N. Loewenstein
IPC分类号： G06F13/38
CPC分类号： H04L45/28 , G06F12/0817 , G06F15/17331 , H04L43/0882 , H04L45/22 , H04L47/11 , H04L47/122 , H04L47/24 , H04L47/527
摘要： Systems and methods for efficient data transport across multiple processors when link utilization is congested. In a multi-node system, each of the nodes measures a congestion level for each of the one or more links connected to it. A source node indicates when each of one or more links to a destination node is congested or each non-congested link is unable to send a particular packet type. In response, the source node sets an indication that it is a candidate for seeking a data forwarding path to send a packet of the particular packet type to the destination node. The source node uses measured congestion levels received from other nodes to search for one or more intermediate nodes. An intermediate node in a data forwarding path has non-congested links for data transport. The source node reroutes data to the destination node through the data forwarding path.
摘要翻译：当链路利用率拥挤时，用于跨多个处理器的高效数据传输的系统和方法。在多节点系统中，每个节点测量与其相连的一个或多个链路中的每一个的拥塞级别。源节点指示到达目的地节点的一个或多个链路中的每一个是何时拥塞，或者每个非拥塞链路不能发送特定分组类型。作为响应，源节点设置它是寻找数据转发路径以将特定分组类型的分组发送到目的地节点的候选者的指示。源节点使用从其他节点接收的测量拥塞级别来搜索一个或多个中间节点。数据转发路径中的中间节点具有用于数据传输的非拥塞链路。源节点通过数据转发路径将数据重新路由到目的节点。

3. 发明授权

US08332729B2 System and method for automatic communication lane failover in a serial link 有权
标题翻译：在串行链路中自动通信通道故障转移的系统和方法
公开(公告)号：US08332729B2
公开(公告)日：2012-12-11
申请号：US12239960
申请日：2008-09-29
申请人： Ramaswamy Sivaramakrishnan , Sebastian Turullols , Stephen E. Phillips
发明人： Ramaswamy Sivaramakrishnan , Sebastian Turullols , Stephen E. Phillips
IPC分类号： H03M13/00
CPC分类号： H04L1/0006 , G06F13/4295 , H04L1/0057
摘要： A system for automatic lane failover includes a first device coupled to a second device via a serial communication link having a plurality of a communication lanes. The devices may communicate by operating the link in a normal mode and a degraded mode. During normal mode operation, the devices may send frames of information to each other via the serial communication link. Each frame of information may include a number of data bits and a number of error protection bits. In response to either device detecting a failure of one or more of the communication lanes, the first device may cause the serial communication link to operate in a degraded mode by removing the one or more failed communication lanes. In addition, each device may reformat and send the frame of information on the remaining communication lanes with fewer data bits and the same number of error protection bits.
摘要翻译：用于自动车道故障转移的系统包括经由具有多个通信车道的串行通信链路耦合到第二设备的第一设备。设备可以通过在正常模式和劣化模式下操作链路进行通信。在正常模式操作期间，设备可以经由串行通信链路相互发送信息帧。每帧信息可以包括多个数据位和多个错误保护位。响应于任一设备检测到一个或多个通信通道的故障，第一设备可以通过去除一个或多个故障通信通道来使得串行通信链路以降级模式操作。此外，每个设备可以重新格式化并且在剩余的通信线路上以更少的数据位和相同数量的错误保护位来发送信息帧。

4. 发明授权

US08269544B2 Power-supply noise suppression using a frequency-locked loop 有权
标题翻译：使用频率锁定环路进行电源噪声抑制
公开(公告)号：US08269544B2
公开(公告)日：2012-09-18
申请号：US12896650
申请日：2010-10-01
申请人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
发明人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
IPC分类号： H03H11/26
CPC分类号： H03L7/18
摘要： An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.
摘要翻译：描述了一种集成电路，其包括基于DCO和关键路径的电源电压的变化来调整集成电路的关键路径的时钟频率的数字控制振荡器（DCO）。该DCO可以包括在包括频率锁定环（FLL）的反馈控制环路中，并且其基于参考频率确定关键路径的平均时钟频率。此外，DCO可以具有可选择的延迟特性，其指定作为电源电压的函数的DCO的延迟灵敏度，从而大致匹配所制造的关键路径的延迟特性。此外，对于具有大于与集成电路的芯片封装相关联的谐振频率的电源电压的变化，时钟频率的调整可以与电源电压和可选延迟特性的变化成比例。

5. 发明申请

US20130311814A1 CONSTANT FREQUENCY ARCHITECTURAL TIMER IN A DYNAMIC CLOCK DOMAIN 有权
标题翻译：动态时钟域中的恒定频率建筑定时器
公开(公告)号：US20130311814A1
公开(公告)日：2013-11-21
申请号：US13472105
申请日：2012-05-15
申请人： Sebastian Turullols , Ali Vahidsafa
发明人： Sebastian Turullols , Ali Vahidsafa
IPC分类号： G06F1/04 , G06F1/12
CPC分类号： G06F1/14 , G06F1/12 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
摘要翻译：本公开的实现涉及一种用于为经变化的核心时钟信号操作的微处理器提供恒定频率定时器信号的装置和/或方法。该装置和/或方法利用码本发生器，例如灰度代码发生器，其操作在允许恒定频率定时器信号比核心时钟频率更快或更慢的参考时钟信号。更具体地，装置和/或方法可以计算先前灰度代码样本之间的差异，并将计算出的差值加到软件可见参考时钟信号上，使得恒定频率定时器信号可以比核心时钟信号更快或更慢。通过使用装置和/或方法，可以根据需要减少核心时钟信号，以在维持计算系统的执行程序之间的同步的同时，使微处理器和采用本文描述的技术的计算系统提供操作功率节省。

6. 发明申请

US20120081157A1 POWER-SUPPLY NOISE SUPPRESSION USING A FREQUENCY-LOCKED LOOP 有权
标题翻译：使用频率锁定环路的电源噪声抑制
公开(公告)号：US20120081157A1
公开(公告)日：2012-04-05
申请号：US12896650
申请日：2010-10-01
申请人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
发明人： David J. Greenhill , Robert P. Masleid , Georgios K. Konstadinidis , King C. Yen , Sebastian Turullols
IPC分类号： H03L7/06
CPC分类号： H03L7/18
摘要： An integrated circuit that includes a digitally controlled oscillator (DCO) that adjusts a clock frequency of a critical path of the integrated circuit based on the variations in a power-supply voltage of the DCO and the critical path is described. This DCO may be included in a feedback control loop that includes a frequency-locked loop (FLL), and which determines an average clock frequency of the critical path based on a reference frequency. Furthermore, the DCO may have a selectable delay characteristic that specifies a delay sensitivity of the DCO as a function of the power-supply voltage, thereby approximately matching a manufactured delay characteristic of the critical path. Additionally, for variations in the power-supply voltage having frequencies greater than a resonance frequency associated with a chip package of the integrated circuit, adjustments of the clock frequency may be proportional to the variations in the power-supply voltage and the selectable delay characteristic.
摘要翻译：描述了一种集成电路，其包括基于DCO和关键路径的电源电压的变化来调整集成电路的关键路径的时钟频率的数字控制振荡器（DCO）。该DCO可以包括在包括频率锁定环（FLL）的反馈控制环路中，并且其基于参考频率确定关键路径的平均时钟频率。此外，DCO可以具有可选择的延迟特性，其指定作为电源电压的函数的DCO的延迟灵敏度，从而大致匹配所制造的关键路径的延迟特性。此外，对于具有大于与集成电路的芯片封装相关联的谐振频率的电源电压的变化，时钟频率的调整可以与电源电压和可选延迟特性的变化成比例。

7. 发明申请

US20100211742A1 CONVEYING CRITICAL DATA IN A MULTIPROCESSOR SYSTEM 有权
标题翻译：在多处理器系统中传输关键数据
公开(公告)号：US20100211742A1
公开(公告)日：2010-08-19
申请号：US12370757
申请日：2009-02-13
申请人： Sebastian Turullols , Sumti Jairath
发明人： Sebastian Turullols , Sumti Jairath
IPC分类号： G06F15/76 , G06F9/06 , G06F12/08
CPC分类号： G06F12/0806 , G06F12/0815 , G06F12/0859
摘要： A system for conveying critical and non-critical words of multiple cache lines includes a first node interface of a first processing node receiving, from a first processor, a first request identifying a critical word of a first cache line and a second request identifying a critical word of a second cache line. The first node interface conveys requests corresponding to the first and second requests to a second node interface of a second processing node. The second node interface receives the corresponding requests and conveys the critical words of the first and second cache lines to the first processing node before conveying non-critical words of the first and second cache lines.
摘要翻译：用于传送多个高速缓存线的关键和非关键词的系统包括第一处理节点的第一节点接口，从第一处理器接收第一请求，其识别第一高速缓存行的关键字，以及识别关键字的第二请求第二个缓存行的字。第一节点接口将对应于第一和第二请求的请求传送到第二处理节点的第二节点接口。第二节点接口接收相应的请求，并且在传送第一和第二高速缓存行的非关键字之前，将第一和第二高速缓存行的关键字传送到第一处理节点。

8. 发明授权

US08990606B2 Constant frequency architectural timer in a dynamic clock domain 有权
标题翻译：动态时钟域中的恒定频率架构定时器
公开(公告)号：US08990606B2
公开(公告)日：2015-03-24
申请号：US13472105
申请日：2012-05-15
申请人： Sebastian Turullols , Ali Vahidsafa
发明人： Sebastian Turullols , Ali Vahidsafa
IPC分类号： G06F1/00 , H03K5/01 , H03L7/00 , G06F1/12 , G06F1/14
CPC分类号： G06F1/14 , G06F1/12 , G06F1/324 , G06F1/3296 , Y02D10/126 , Y02D10/172
摘要： Implementations of the present disclosure involve an apparatus and/or method for providing a constant frequency timer signal for a microprocessor that operates with varying core clock signals. The apparatus and/or method utilizes a code generator, such as a gray code generator, operating on a reference clock signal that allows the constant frequency timer signal to be either faster or slower than the core clock frequency. More particularly, the apparatus and/or method may compute a difference between previous gray code samples and add the calculated difference to a software visible reference clock signal such that constant frequency timer signal may be faster or slower than the core clock signal. Through the use of the apparatus and/or method, a core clock signal may be reduced as needed to provide operational power savings to the microprocessor and the computing system employing the techniques described herein, while maintaining synchronization between the executing programs of the computing system.
摘要翻译：本公开的实现涉及一种用于为经变化的核心时钟信号操作的微处理器提供恒定频率定时器信号的装置和/或方法。该装置和/或方法利用码本发生器，例如灰度代码发生器，其操作在允许恒定频率定时器信号比核心时钟频率更快或更慢的参考时钟信号。更具体地，装置和/或方法可以计算先前灰度代码样本之间的差异，并将计算出的差值加到软件可见参考时钟信号上，使得恒定频率定时器信号可以比核心时钟信号更快或更慢。通过使用装置和/或方法，可以根据需要减少核心时钟信号，以在维持计算系统的执行程序之间的同步的同时，使微处理器和采用本文描述的技术的计算系统提供操作功率节省。

9. 发明申请

US20140062548A1 WIDE-RANGE GLITCH-FREE ASYNCHRONOUS CLOCK SWITCH 有权
标题翻译：宽屏无刷异步时钟开关
公开(公告)号：US20140062548A1
公开(公告)日：2014-03-06
申请号：US13604795
申请日：2012-09-06
申请人： Changku Hwang , Sebastian Turullols , Daisy Jian , Ali Vahidsafa
发明人： Changku Hwang , Sebastian Turullols , Daisy Jian , Ali Vahidsafa
IPC分类号： H03L7/00 , H03L7/06
CPC分类号： H03K5/135
摘要： Embodiments include systems and methods for asynchronous, glitch-free clock switching across a wide range of clock frequencies with minimal clock down time. Embodiments effectively provide two stages of synchronization across two independent clock domains. In a first synchronization stage, a received, asynchronous clock select signal is translated into a synchronized clock select signal that is effectively synchronous with respect to a first clock domain and is still effectively asynchronous with respect to a second clock domain. In a second synchronization stage, the synchronized clock select signal is resynchronized so as to be effectively synchronous with respect to the second clock domain. The synchronized select signal can be used to disable the clock of the first clock domain, and the resynchronized clock select signal can be used to enable the clock of the second clock domain.
摘要翻译：实施例包括用于在具有最小时钟停机时间的宽范围的时钟频率上进行异步，无毛刺时钟切换的系统和方法。实施例有效地提供跨两个独立时钟域的两个阶段的同步。在第一同步阶段，接收到的异步时钟选择信号被转换成相对于第一时钟域有效同步的同步时钟选择信号，并且相对于第二时钟域仍然有效地是异步的。在第二同步级中，同步的时钟选择信号被重新同步，以便相对于第二时钟域有效地同步。同步选择信号可用于禁用第一时钟域的时钟，并且重新同步的时钟选择信号可用于启用第二时钟域的时钟。

10. 发明申请

US20120218034A1 VOLTAGE CALIBRATION METHOD AND APPARATUS 审中-公开
标题翻译：电压校准方法和装置
公开(公告)号：US20120218034A1
公开(公告)日：2012-08-30
申请号：US13036285
申请日：2011-02-28
申请人： Sebastian Turullols , Ali Vahidsafa , David Greenhill
发明人： Sebastian Turullols , Ali Vahidsafa , David Greenhill
IPC分类号： G05F1/10
CPC分类号： G06F1/28
摘要： A method and apparatus for power supply calibration to reduce voltage guardbands is disclosed. In one embodiment, an integrated circuit (IC) includes a voltage measurement unit configured to measure an operating voltage during a start-up procedure. The IC further includes a comparator configured to compare the measured operating voltage to a target voltage. The comparator is further configured to cause a change to a supply voltage (upon which the operating voltage is based) if the operating voltage is not within a target voltage range and to repeat the measurement of the operating voltage. If the operating voltage is within the target voltage range, the comparator is configured to inhibit further changes to the operating voltage.
摘要翻译：公开了一种用于降低电压保护带的电源校准的方法和装置。在一个实施例中，集成电路（IC）包括被配置为在启动过程期间测量工作电压的电压测量单元。 IC还包括比较器，其被配置为将测量的工作电压与目标电压进行比较。如果工作电压不在目标电压范围内并且重复测量工作电压，比较器还被配置为引起电源电压（基于工作电压的基准）的改变。如果工作电压在目标电压范围内，则比较器被配置为禁止进一步改变工作电压。

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