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1. 发明授权

US07153778B2 Methods of forming openings, and methods of forming container capacitors 有权
公开(公告)号：US07153778B2
公开(公告)日：2006-12-26
申请号：US10783843
申请日：2004-02-20
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

2. 发明授权

US07538036B2 Methods of forming openings, and methods of forming container capacitors 失效
标题翻译：形成开口的方法，以及形成容器电容器的方法
公开(公告)号：US07538036B2
公开(公告)日：2009-05-26
申请号：US11216759
申请日：2005-08-31
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Yoshiki Hishiro , Ulrich C. Boettiger , Richard D. Holscher
IPC分类号： H01L21/3205
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

3. 发明授权

US07321149B2 Capacitor structures, and DRAM arrays 有权
标题翻译：电容结构和DRAM阵列
公开(公告)号：US07321149B2
公开(公告)日：2008-01-22
申请号：US11187210
申请日：2005-07-22
申请人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
发明人： Brett W. Busch , Luan C. Tran , Ardavan Niroomand , Fred D. Fishburn , Richard D. Holscher
IPC分类号： H01L29/72
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

4. 发明授权

US08598043B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US08598043B2
公开(公告)日：2013-12-03
申请号：US12886459
申请日：2010-09-20
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且在第一和第二开口内形成电绝缘材料。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

5. 发明授权

US07799694B2 Methods of forming semiconductor constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US07799694B2
公开(公告)日：2010-09-21
申请号：US11402659
申请日：2006-04-11
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/302
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings. The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且在第一和第二开口内形成电绝缘材料。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

6. 发明申请

US20060009042A1 Methods of forming openings, and methods of forming container capacitors 失效
公开(公告)号：US20060009042A1
公开(公告)日：2006-01-12
申请号：US11216759
申请日：2005-08-31
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
IPC分类号： H01L21/302 , H01L21/31
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.

7. 发明申请

US20050186802A1 Methods of Forming Openings, And Methods of Forming Container Capacitors 有权
标题翻译：形成开口的方法和形成容器电容器的方法
公开(公告)号：US20050186802A1
公开(公告)日：2005-08-25
申请号：US10783843
申请日：2004-02-20
申请人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
发明人： Brett Busch , Luan Tran , Ardavan Niroomand , Fred Fishburn , Yoshiki Hishiro , Ulrich Boettiger , Richard Holscher
IPC分类号： H01L21/02 , H01L21/033 , H01L21/302 , H01L21/311 , H01L21/461 , H01L21/8234 , H01L21/8242 , H01L21/8244 , H01L27/108 , H01L29/76
CPC分类号： H01L21/0332 , H01L21/0337 , H01L21/31144 , H01L27/10852 , H01L28/91 , Y10S438/942 , Y10S438/946
摘要： A patterned mask can be formed as follows. A first patterned photoresist is formed over a masking layer and utilized during a first etch into the masking layer. The first etch extends to a depth in the masking layer that is less than entirely through the masking layer. A second patterned photoresist is subsequently formed over the masking layer and utilized during a second etch into the masking layer. The combined first and second etches form openings extending entirely through the masking layer and thus form the masking layer into the patterned mask. The patterned mask can be utilized to form a pattern in a substrate underlying the mask. The pattern formed in the substrate can correspond to an array of capacitor container openings. Capacitor structure can be formed within the openings. The capacitor structures can be incorporated within a DRAM array.
摘要翻译：图案化掩模可以如下形成。在掩模层上形成第一图案化的光致抗蚀剂，并在第一蚀刻进入掩模层期间使用。第一蚀刻延伸到掩模层中的深度不到完全通过掩模层的深度。随后在掩模层上形成第二图案化的光致抗蚀剂，并在第二次蚀刻进入掩模层期间利用。组合的第一和第二蚀刻形成完全延伸穿过掩模层的开口，从而在掩模层中形成掩模层。图案化掩模可以用于在掩模下面的衬底中形成图案。形成在基板中的图案可以对应于电容器容器开口的阵列。可以在开口内形成电容结构。电容器结构可以并入DRAM阵列中。

8. 发明授权

US07821142B2 Intermediate semiconductor device structures 有权
标题翻译：中间半导体器件结构
公开(公告)号：US07821142B2
公开(公告)日：2010-10-26
申请号：US12145022
申请日：2008-06-24
申请人： Richard D. Holscher , Ardavan Niroomand
发明人： Richard D. Holscher , Ardavan Niroomand
IPC分类号： H01L23/544
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , Y10S438/942 , Y10S438/947 , Y10S438/975 , H01L2924/00
摘要： An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.
摘要翻译：对准标记掩模元件在制造衬底的后续处理期间保护底层对准标记。对准标记掩模元件与从曝光到能级时显示图案反转的双色光致抗蚀剂形成光掩模同时形成。在对准标记上方的双色光致抗蚀剂的一部分暴露于足以将正色调抗拒反转到负色调的能量，该负色调在显影之后保持在对准标记之上。双色光致抗蚀剂的其余部分以较低的能级暴露在掩模版上，并被图案化以限定用于形成半导体器件特征的光掩模的孔径位置。另外，公开了用于制造衬底和中间半导体器件的光掩模。还公开了形成光掩模和中间半导体器件结构的方法。

9. 发明申请

US20110008970A1 Methods of Forming Semiconductor Constructions 有权
标题翻译：形成半导体结构的方法
公开(公告)号：US20110008970A1
公开(公告)日：2011-01-13
申请号：US12886459
申请日：2010-09-20
申请人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
发明人： Ramakanth Alapati , Ardavan Niroomand , Gurtej S. Sandhu , Luan C. Tran
IPC分类号： H01L21/31
CPC分类号： H01L21/3086 , H01L21/0337 , H01L21/76232 , H01L27/105 , H01L27/1052
摘要： The invention includes methods of forming isolation regions for semiconductor constructions. A hard mask can be formed and patterned over a semiconductor substrate, with the patterned hard mask exposing a region of the substrate. Such exposed region can be etched to form a first opening having a first width. The first opening is narrowed with a conformal layer of carbon-containing material. The conformal layer is punched through to expose substrate along a bottom of the narrowed opening. The exposed substrate is removed to form a second opening which joins to the first opening, and which has a second width less than the first width. The carbon-containing material is then removed from within the first opening, and electrically insulative material is formed within the first and second openings The electrically insulative material can substantially fill the first opening, and leave a void within the second opening.
摘要翻译：本发明包括形成用于半导体结构的隔离区域的方法。可以在半导体衬底上形成并图案化硬掩模，其中图案化的硬掩模暴露衬底的区域。可以蚀刻这样的暴露区域以形成具有第一宽度的第一开口。第一个开口用含碳材料的共形层变窄。穿过保形层以沿着狭窄的开口的底部露出衬底。去除暴露的衬底以形成连接到第一开口的第二开口，并且具有小于第一宽度的第二宽度。然后从第一开口内去除含碳材料，并且电绝缘材料形成在第一和第二开口内。电绝缘材料可以基本上填充第一开口，并在第二开口内留下空隙。

10. 发明申请

US20080251951A1 USE OF A DUAL TONE RESIST TO FORM PHOTOMASKS AND INTERMEDIATE SEMICONDUCTOR DEVICE STRUCTURES 有权
标题翻译：使用双音色形成光电子和中间半导体器件结构
公开(公告)号：US20080251951A1
公开(公告)日：2008-10-16
申请号：US12145022
申请日：2008-06-24
申请人： Richard D. Holscher , Ardavan Niroomand
发明人： Richard D. Holscher , Ardavan Niroomand
IPC分类号： H01L23/544 , G03F1/16
CPC分类号： H01L23/544 , H01L2223/54426 , H01L2223/54453 , H01L2223/54493 , H01L2924/0002 , Y10S438/942 , Y10S438/947 , Y10S438/975 , H01L2924/00
摘要： An alignment mark mask element protects an underlying alignment mark during subsequent processing of a fabrication substrate. The alignment mark mask element is formed concurrent with formation of a photomask from a dual-tone photoresist that exhibits a pattern reversal upon exposure to an energy level. A portion of the dual-tone photoresist above the alignment mark is exposed to an energy sufficient to reverse a positive tone resist to a negative tone, which remains above the alignment mark after developing. The remainder of the dual-tone photoresist is exposed through a reticle at a lesser energy level and patterned to define aperture locations of a photomask for formation of semiconductor device features. In addition, a photomask for use on a fabrication substrate and an intermediate semiconductor device are disclosed. Methods of forming a photomask and an intermediate semiconductor device structure are also disclosed.
摘要翻译：对准标记掩模元件在制造衬底的后续处理期间保护底层对准标记。对准标记掩模元件与从曝光到能级时显示图案反转的双色光致抗蚀剂形成光掩模同时形成。在对准标记上方的双色光致抗蚀剂的一部分暴露于足以将正色调抗拒反转到负色调的能量，该负色调在显影之后保持在对准标记之上。双色光致抗蚀剂的其余部分以较小的能级暴露在掩模版上，并被图案化以限定用于形成半导体器件特征的光掩模的孔径位置。另外，公开了用于制造衬底和中间半导体器件的光掩模。还公开了形成光掩模和中间半导体器件结构的方法。

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