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1. 发明授权

US06173387B2 Interleaved exchange in a network mesh 失效
标题翻译：交织网络中的交织
公开(公告)号：US06173387B2
公开(公告)日：2001-01-09
申请号：US08773262
申请日：1996-12-23
申请人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
发明人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
IPC分类号： G06F1500
CPC分类号： G06F15/17337
摘要： A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.
摘要翻译：一种用于在具有由四个象限定义的节点阵列的网状网络内交换信息的方法。该方法包括将信息从一个象限中的一组节点交换到位于相邻象限中的一组节点的初始步骤。信息交换同时发生在阵列内的垂直和水平方向上。然后在相同的象限和子级别内的节点之间交换信息。

2. 发明授权

US06356992B1 Method and apparatus for interleaved exchange in a network mesh 失效
标题翻译：网络网格中交织交换的方法和装置
公开(公告)号：US06356992B1
公开(公告)日：2002-03-12
申请号：US09624287
申请日：2000-07-24
申请人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
发明人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
IPC分类号： G06F1500
CPC分类号： G06F15/17337
摘要： A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.
摘要翻译：一种用于在具有由四个象限定义的节点阵列的网状网络内交换信息的方法。该方法包括将信息从一个象限中的一组节点交换到位于相邻象限中的一组节点的初始步骤。信息交换同时发生在阵列内的垂直和水平方向上。然后在相同的象限和子级别内的节点之间交换信息。

3. 发明授权

US06948048B2 Method and apparatus for interleaved exchange in a network mesh 失效
标题翻译：网络网格中交织交换的方法和装置
公开(公告)号：US06948048B2
公开(公告)日：2005-09-20
申请号：US10188956
申请日：2002-07-02
申请人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
发明人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
IPC分类号： G06F15/173 , G06F15/00
CPC分类号： G06F15/17337
摘要： A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.
摘要翻译：一种用于在具有由四个象限定义的节点阵列的网状网络内交换信息的方法。该方法包括将信息从一个象限中的一组节点交换到位于相邻象限中的一组节点的初始步骤。信息交换同时发生在阵列内的垂直和水平方向上。然后在相同的象限和子级别内的节点之间交换信息。

4. 发明授权

US06460128B1 Mesh network with method and apparatus for interleaved binary exchange 失效
标题翻译：网状网络与交织二进制交换的方法和装置
公开(公告)号：US06460128B1
公开(公告)日：2002-10-01
申请号：US09879030
申请日：2001-06-12
申请人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
发明人： Brent Baxter , Stuart Hawkinson , Satyanarayan Gupta
IPC分类号： G06F1500
CPC分类号： G06F15/17337
摘要： A method for exchanging information within a mesh network that has an array of nodes defined by four quadrants. The method includes the initial step of exchanging information from a set of nodes in one quadrant to a set of nodes located in an adjacent quadrant. The exchange of information simultaneously occurs in both a vertical and horizontal direction within the array. Information is then exchanged between nodes within the same quadrant and subquadrants.
摘要翻译：一种用于在具有由四个象限定义的节点阵列的网状网络内交换信息的方法。该方法包括将信息从一个象限中的一组节点交换到位于相邻象限中的一组节点的初始步骤。信息交换同时发生在阵列内的垂直和水平方向上。然后在相同的象限和子级别内的节点之间交换信息。

5. 发明申请

US20050114560A1 Tightly coupled and scalable memory and execution unit architecture 审中-公开
公开(公告)号：US20050114560A1
公开(公告)日：2005-05-26
申请号：US10972083
申请日：2004-10-21
申请人： Ron Coleman , Brent LeBack , Stuart Hawkinson , Richard Rubinstein
发明人： Ron Coleman , Brent LeBack , Stuart Hawkinson , Richard Rubinstein
IPC分类号： G06F9/38 , H04N7/26 , H04N7/50 , G06F13/28
CPC分类号： G06F9/3897 , G06F9/3879 , G06F2213/0038 , H04N19/423 , H04N19/61
摘要： An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit. The execution unit, local fast memory and local address generator form a fast memory path that is not dependent upon the slower data path between the execution unit and shared memory. The fast memory path provides for fast execution of scalar operations in the execution unit and rapid state storage and retrieval for operations in the execution unit.

6. 发明授权

US06895452B1 Tightly coupled and scalable memory and execution unit architecture 失效
标题翻译：紧密耦合和可扩展的内存和执行单元架构
公开(公告)号：US06895452B1
公开(公告)日：2005-05-17
申请号：US09174057
申请日：1998-10-16
申请人： Ron Coleman , Brent LeBack , Stuart Hawkinson , Richard Rubinstein
发明人： Ron Coleman , Brent LeBack , Stuart Hawkinson , Richard Rubinstein
IPC分类号： G06F9/38 , H04N7/26 , H04N7/50 , G06F15/76
CPC分类号： G06F9/3897 , G06F9/3879 , G06F2213/0038 , H04N19/423 , H04N19/61
摘要： An architecture is shown where an execution unit is tightly coupled to a shared, reconfigurable memory system. Sequence control signals drive a DMA controller and address generator to control the transfer of data from the shared memory to a bus interface unit (BIU). The sequence control signals also drive a data controller and address generator which controls transfer of data from the shared memory to an execution unit interface (EUI). The EUI is connected to the execution unit operates under control of the data controller and address generator to transfer vector data to and from the shared memory. The shared memory is configured to swap memory space in between the BIU and the execution unit so as to support continuous execution and I/O. A local fast memory is coupled to the execution unit. A local address generator controls the transfer of scalar data between the local fast memory and the execution unit. The execution unit, local fast memory and local address generator form a fast memory path that is not dependent upon the slower data path between the execution unit and shared memory. The fast memory path provides for fast execution of scalar operations in the execution unit and rapid state storage and retrieval for operations in the execution unit.
摘要翻译：示出了一种结构，其中执行单元紧密耦合到共享的可重新配置的存储器系统。顺序控制信号驱动DMA控制器和地址发生器来控制数据从共享存储器传输到总线接口单元（BIU）。序列控制信号还驱动数据控制器和地址生成器，其控制数据从共享存储器传送到执行单元接口（EUI）。连接到执行单元的EUI在数据控制器和地址生成器的控制下操作，以将向量数据传送到和从共享存储器传送。共享内存配置为交换BIU和执行单元之间的内存空间，以支持连续执行和I / O。本地快速存储器耦合到执行单元。本地地址生成器控制本地快速存储器和执行单元之间的标量数据传输。执行单元，本地快速存储器和本地地址生成器形成快速存储器路径，其不依赖于执行单元和共享存储器之间较慢的数据路径。快速存储器路径提供了执行单元中的标量操作的快速执行以及用于执行单元中的操作的快速状态存储和检索。

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