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1. 发明申请

US20080181034A1 MEMORY SYSTEM WITH REDUNDANT RAM MEMORY CELLS HAVING A DIFFERENT DESIGNED CELL CIRCUIT TOPOLOGY 有权
标题翻译：具有冗余RAM记忆体的存储系统具有不同的设计细胞电路拓扑学
公开(公告)号：US20080181034A1
公开(公告)日：2008-07-31
申请号：US11627445
申请日：2007-01-26
申请人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
发明人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C11/41 , G11C11/412 , G11C29/816
摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
摘要翻译：一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。

2. 发明授权

US07684264B2 Memory system with RAM array and redundant RAM memory cells having a different designed cell circuit topology than cells of non redundant RAM array 有权
标题翻译：具有RAM阵列和冗余RAM存储单元的存储器系统具有与非冗余RAM阵列的单元不同的设计单元电路拓扑
公开(公告)号：US07684264B2
公开(公告)日：2010-03-23
申请号：US11627445
申请日：2007-01-26
申请人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
发明人： Bradford L. Hunter , James D. Burnett , Andrew C. Russell , Shayan Zhang
IPC分类号： G11C7/00
CPC分类号： G11C29/846 , G11C11/41 , G11C11/412 , G11C29/816
摘要： A memory system including a random access memory (RAM) array and a corresponding redundant RAM array which stores information redundant to the RAM array, where a designed cell circuit topology of cells within the redundant RAM array differs from a designed cell circuit topology of cells within the RAM array. The redundant RAM array is selectively accessed when accessing the RAM array to store data to the redundant RAM array for failed cells of the RAM array.
摘要翻译：一种存储器系统，包括随机存取存储器（RAM）阵列和相应的冗余RAM阵列，其存储对RAM阵列冗余的信息，其中冗余RAM阵列内的单元的设计单元电路拓扑不同于设计的单元的单元电路拓扑 RAM阵列。当访问RAM阵列时，有选择地访问冗余RAM阵列，以将数据存储到RAM阵列的故障单元的冗余RAM阵列中。

3. 发明授权

US07793172B2 Controlled reliability in an integrated circuit 有权
标题翻译：控制集成电路中的可靠性
公开(公告)号：US07793172B2
公开(公告)日：2010-09-07
申请号：US11536342
申请日：2006-09-28
申请人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
发明人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
IPC分类号： G11C29/00 , G11C11/4074
CPC分类号： G11C29/42 , G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.
摘要翻译：提供了用于配置与包括可寻址单元的存储器阵列的至少一部分相关联的特性的方法和系统。一方面，一种用于控制存储器阵列的电源电压的方法包括使用耦合到存储器阵列的第一电源电压来检测在对存储器阵列的可寻址单元执行读取操作时是否发生错误。该方法还包括增加误差计数器以跟踪与存储器阵列相关联的误差计数，并且如果误差计数等于或超过存储器阵列的误差阈值，则将存储器阵列切换到第二电源电压。该方法还包括基于至少一个条件，将存储器阵列切换到第一电源电压并将错误计数器重置为初始值。

4. 发明申请

US20080091990A1 CONTROLLED RELIABILITY IN AN INTEGRATED CIRCUIT 有权
标题翻译：集成电路中控制的可靠性
公开(公告)号：US20080091990A1
公开(公告)日：2008-04-17
申请号：US11536342
申请日：2006-09-28
申请人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
发明人： Klas M. Bruce , Andrew C. Russell , Shayan Zhang , Bradford L. Hunter
IPC分类号： G11C29/00
CPC分类号： G11C29/42 , G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028
摘要： Methods and systems for configuring characteristics associated with at least one portion of a memory array comprising addressable units are provided. In one aspect, a method for controlling a power supply voltage for a memory array comprises detecting whether an error occurred in performing a read operation on an addressable unit of the memory array using a first power supply voltage coupled to the memory array. The method further comprises incrementing an error counter for tracking an error count associated with the memory array and switching the memory array to a second power supply voltage if the error count is equal to or exceeds an error threshold for the memory array. The method further comprises, based on at least one condition, switching the memory array to the first power supply voltage and resetting the error counter to an initial value.
摘要翻译：提供了用于配置与包括可寻址单元的存储器阵列的至少一部分相关联的特性的方法和系统。一方面，一种用于控制存储器阵列的电源电压的方法包括使用耦合到存储器阵列的第一电源电压来检测在对存储器阵列的可寻址单元执行读取操作时是否发生错误。该方法还包括增加误差计数器以跟踪与存储器阵列相关联的误差计数，并且如果误差计数等于或超过存储器阵列的误差阈值，则将存储器阵列切换到第二电源电压。该方法还包括基于至少一个条件，将存储器阵列切换到第一电源电压并将错误计数器重置为初始值。

5. 发明申请

US20080082873A1 MINIMUM MEMORY OPERATING VOLTAGE TECHNIQUE 有权
标题翻译：最小存储器工作电压技术
公开(公告)号：US20080082873A1
公开(公告)日：2008-04-03
申请号：US11468458
申请日：2006-08-30
申请人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
发明人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C29/00
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译：一种方法包括具有存储器的集成电路。存储器工作在工作电压。确定存储器的最小工作电压的值。最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。最小电压只能用于集成电路内部，也可以在用户外部使用。

6. 发明授权

US07523373B2 Minimum memory operating voltage technique 有权
标题翻译：最低内存工作电压技术
公开(公告)号：US07523373B2
公开(公告)日：2009-04-21
申请号：US11468458
申请日：2006-08-30
申请人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
发明人： Andrew C. Russell , David R. Bearden , Bradford L. Hunter , Shayan Zhang
IPC分类号： G01R31/30
CPC分类号： G11C5/147 , G11C29/02 , G11C29/021 , G11C29/028 , G11C29/50 , G11C29/50016 , G11C2029/5004
摘要： A method includes an integrated circuit with a memory. The memory operates with an operating voltage. A value of a minimum operating voltage of the memory is determined. The value of the minimum operating voltage is stored in a non-volatile memory location that maybe a non-volatile register. This minimum operating voltage information can then be used in determining when an alternative power supply voltage may be switched to the memory or ensuring that the minimum voltage is otherwise met. The minimum voltage can be used only internal to the integrated circuit or also provided externally to a user.
摘要翻译：一种方法包括具有存储器的集成电路。存储器工作在工作电压。确定存储器的最小工作电压值。最小工作电压的值存储在可能是非易失性寄存器的非易失性存储器位置。然后可以使用该最小工作电压信息来确定什么时候可以将替代电源电压切换到存储器或确保以其他方式满足最小电压。最小电压只能用于集成电路内部，也可以在用户外部使用。

7. 发明授权

US08077533B2 Memory and method for sensing data in a memory using complementary sensing scheme 有权
标题翻译：用于使用互补感测方案检测存储器中的数据的存储器和方法
公开(公告)号：US08077533B2
公开(公告)日：2011-12-13
申请号：US11337783
申请日：2006-01-23
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/12 , G11C7/06 , G11C7/08 , G11C7/22
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

8. 发明授权

US08456935B2 Memory and method for sensing data in a memory using complementary sensing scheme 有权
标题翻译：用于使用互补感测方案检测存储器中的数据的存储器和方法
公开(公告)号：US08456935B2
公开(公告)日：2013-06-04
申请号：US13297415
申请日：2011-11-16
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/12 , G11C7/06 , G11C7/08 , G11C7/22
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

9. 发明申请

US20120063249A1 MEMORY AND METHOD FOR SENSING DATA IN A MEMORY USING COMPLEMENTARY SENSING SCHEME 有权
标题翻译：使用补充感测方案在存储器中感测数据的存储器和方法
公开(公告)号：US20120063249A1
公开(公告)日：2012-03-15
申请号：US13297415
申请日：2011-11-16
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/12
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

10. 发明授权

US07158432B1 Memory with robust data sensing and method for sensing data 有权
标题翻译：具有强大数据感测的存储器和用于感测数据的方法
公开(公告)号：US07158432B1
公开(公告)日：2007-01-02
申请号：US11218135
申请日：2005-09-01
申请人： Bradford L. Hunter , Shayan Zhang
发明人： Bradford L. Hunter , Shayan Zhang
IPC分类号： G11C7/00 , G11C8/00
CPC分类号： G11C7/12 , G11C7/065 , G11C7/1048 , G11C7/18
摘要： A memory (100) includes first (116) and second (118) sense amplifiers, a first logic gate (120), a first three-state driver (130), and a latch (180). The first sense amplifier (116) is coupled to a first local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the first local data line. The second sense amplifier (118) is coupled to a second local data line and has an output terminal for providing a signal indicative of a state of a selected memory cell on the second local data line. The first three-state driver (130) has a data input terminal coupled to the output terminal of the first logic gate (120), a control input terminal for receiving a first select signal, and an output terminal coupled to a global data line. The latch (180) has an input/output terminal coupled to the global data line (170).
摘要翻译：存储器（100）包括第一（116）和第二（118）读出放大器，第一逻辑门（120），第一三状态驱动器（130）和锁存器（180）。第一读出放大器（116）耦合到第一本地数据线，并且具有用于在第一本地数据线上提供指示所选存储器单元的状态的信号的输出端。第二读出放大器（118）耦合到第二本地数据线，并且具有用于提供表示第二本地数据线上所选存储单元的状态的信号的输出端。第一三态驱动器（130）具有耦合到第一逻辑门（120）的输出端的数据输入端，用于接收第一选择信号的控制输入端和耦合到全局数据线的输出端。锁存器（180）具有耦合到全局数据线（170）的输入/输出端子。

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