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1. 发明授权

US07675806B2 Low voltage memory device and method thereof 有权
标题翻译：低电压存储器件及其方法
公开(公告)号：US07675806B2
公开(公告)日：2010-03-09
申请号：US11435942
申请日：2006-05-17
申请人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russell , Shayan Zhang , Michael Snyder
发明人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russell , Shayan Zhang , Michael Snyder
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C5/147
摘要： A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
摘要翻译：公开了一种具有低电压存储器件的器件。该设备包括具有第一存储器拓扑的第一存储器和具有第二存储器拓扑的第二存储器，其中两个存储器位于集成电路中。第一存储器是相对高密度存储器件，能够存储相对于第二存储器的大量数据。第二存储器是能够相对于可以访问第一存储器的电压的低电压访问的低电压存储器件。因此，当集成电路处于低电压工作模式时，第二存储器可访问，这可以表示第一存储器或集成电路的其它部分的数据保持状态（睡眠状态）。因此，该器件能够在正常或主动操作模式下将大量数据存储在高密度存储器中，并且还可以在低电压操作模式期间访问低电压存储器。

2. 发明申请

US20070280026A1 Low voltage memory device and method thereof 有权
标题翻译：低电压存储器件及其方法
公开(公告)号：US20070280026A1
公开(公告)日：2007-12-06
申请号：US11435942
申请日：2006-05-17
申请人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
发明人： Bradford Hunter , David Burnett , Troy Cooper , Prashant Kenkare , Ravindraj Ramaraju , Andrew Russel , Shayan Zhang , Michael Snyder
IPC分类号： G11C5/14
CPC分类号： G11C5/143 , G11C5/147
摘要： A device is disclosed having a low-voltage memory device. The device includes a first memory having a first memory topology and a second memory having a second memory topology, with both memories located in an integrated circuit. The first memory is a relatively high-density memory device, capable of storing large amounts of data relative to the second memory. The second memory is a low-voltage memory device capable of being accessed at low-voltages relative to the voltage at which the first memory can be accessed. Accordingly, the second memory is accessible when the integrated circuit is placed in a low-voltage mode of operation, which may represent a data retention state (sleep state) for the first memory or other portions of the integrated circuit. Thus, the device is able to store large amounts of data in the high density memory in a normal or active mode of operation, and also have access to the low-voltage memory during the low-voltage mode of operation.
摘要翻译：公开了一种具有低电压存储器件的器件。该设备包括具有第一存储器拓扑的第一存储器和具有第二存储器拓扑的第二存储器，其中两个存储器位于集成电路中。第一存储器是相对高密度存储器件，能够存储相对于第二存储器的大量数据。第二存储器是能够相对于可以访问第一存储器的电压的低电压访问的低电压存储器件。因此，当集成电路处于低电压工作模式时，第二存储器可访问，这可以表示第一存储器或集成电路的其它部分的数据保持状态（睡眠状态）。因此，该设备能够在正常或主动操作模式下将大量数据存储在高密度存储器中，并且还可以在低电压操作模式期间访问低电压存储器。

3. 发明申请

US20080019206A1 INTEGRATED CIRCUIT HAVING A MEMORY WITH LOW VOLTAGE READ/WRITE OPERATION 有权
标题翻译：具有低电压读/写操作的存储器的集成电路
公开(公告)号：US20080019206A1
公开(公告)日：2008-01-24
申请号：US11863961
申请日：2007-09-28
申请人： Prashant Kenkare , Andrew Russell , David Bearden , James Burnett , Troy Cooper , Shayan Zhang
发明人： Prashant Kenkare , Andrew Russell , David Bearden , James Burnett , Troy Cooper , Shayan Zhang
IPC分类号： G11C5/14
CPC分类号： G11C11/417 , G11C5/147 , G11C11/419
摘要： An integrated circuit with a low voltage read/write operation is provided. The integrated circuit may include a processor and a plurality of memory cells organized in rows and columns and coupled to the processor, wherein a row of memory cells comprises a word line and all of the memory cells coupled to the word line, and wherein a column of memory cells comprises a bit line and all of the memory cells coupled to the bit line. The integrated circuit may further include a first power supply voltage terminal for receiving a first power supply voltage, wherein the first power supply voltage is provided to power the processor, and wherein the first power supply voltage is provided to power the plurality of memory cells during a first access operation of the plurality of memory cells. The integrated circuit may further include a second power supply voltage terminal for receiving a second power supply voltage higher than the first power supply voltage, wherein the second power supply voltage is provided to power the plurality of memory cells during a second access operation of the plurality of memory cells.
摘要翻译：提供具有低电压读/写操作的集成电路。集成电路可以包括处理器和以行和列组织并且耦合到处理器的多个存储单元，其中存储单元行包括字线和耦合到字线的所有存储器单元，并且其中列的存储器单元包括位线和耦合到位线的所有存储器单元。集成电路还可以包括用于接收第一电源电压的第一电源电压端子，其中提供第一电源电压以为处理器供电，并且其中提供第一电源电压以在多个存储器单元期间供电多个存储单元的第一访问操作。集成电路还可以包括用于接收高于第一电源电压的第二电源电压的第二电源电压端子，其中提供第二电源电压以在多个存储器单元的第二访问操作期间为多个存储器单元供电的记忆细胞。

4. 发明申请

US20070171747A1 Memory and method for sensing data in a memory using complementary sensing scheme 有权
标题翻译：用于使用互补感测方案检测存储器中的数据的存储器和方法
公开(公告)号：US20070171747A1
公开(公告)日：2007-07-26
申请号：US11337783
申请日：2006-01-23
申请人： Bradford Hunter , Shayan Zhang
发明人： Bradford Hunter , Shayan Zhang
IPC分类号： G11C7/02
CPC分类号： G11C7/08 , G11C7/065 , G11C11/413 , G11C2207/005
摘要： In a memory (100), a local data line pair (116, 118) is precharged to a first logic state and a global data line pair (101, 104) is precharged to a second logic state. A selected memory cell is coupled to the local data line pair (116, 118) to develop a differential local data line voltage. The differential local data line voltage is subsequently amplified to form an amplified differential local data line voltage. A selected one of the global data line pair (101, 104) is driven to the first logic state in response to the amplified differential local data line voltage to form a differential global data line voltage.
摘要翻译：在存储器（100）中，本地数据线对（116,118）被预充电到第一逻辑状态，并且全局数据线对（101,104）被预充电到第二逻辑状态。所选择的存储器单元耦合到本地数据线对（116,118）以形成差分本地数据线电压。差分局部数据线电压随后被放大以形成放大的差分局部数据线电压。全局数据线对（101,104）中选择的一个被响应于放大的差分本地数据线电压被驱动到第一逻辑状态以形成差分全局数据线电压。

5. 发明授权

US09343183B2 Memory device retention mode based on error information 有权
标题翻译：基于错误信息的内存设备保留模式
公开(公告)号：US09343183B2
公开(公告)日：2016-05-17
申请号：US14463674
申请日：2014-08-20
申请人： Ziyu Guo , Xiangming Kong , Shayan Zhang
发明人： Ziyu Guo , Xiangming Kong , Shayan Zhang
IPC分类号： G11C29/50 , G11C29/52 , G06F1/32 , G11C5/14 , G11C11/417 , G11C29/04
CPC分类号： G11C29/50016 , G06F1/3275 , G06F1/3296 , G11C5/147 , G11C11/417 , G11C29/50004 , G11C29/52 , G11C2029/0409 , Y02D10/14 , Y02D10/172
摘要： A controller for a memory device has a power control section to control power to a memory element in an operation mode and in a retention mode. A monitoring section receives and monitors error information and a storage section stores a retention parameter. In the operation mode, the power control section causes an operation voltage to be applied to the memory element, and in the retention mode, the power control section causes a time-varying voltage to be applied to the memory. The power control section also causes the voltage across the memory element to change in the retention mode between a first retention voltage and a second retention voltage based on the retention parameter.
摘要翻译：用于存储器件的控制器具有功率控制部分，用于在操作模式和保持模式下控制存储元件的功率。监视部分接收和监视错误信息，并且存储部分存储保留参数。在操作模式中，功率控制部分使得存储元件施加操作电压，并且在保持模式下，功率控制部分使时变电压施加到存储器。功率控制部分还使得存储元件两端的电压基于保持参数在第一保持电压和第二保持电压之间的保持模式中改变。

6. 发明申请

US20140040688A1 LOW POWER SCAN FLIP-FLOP CELL 有权
标题翻译：低功率扫描FLIP-FLOP细胞
公开(公告)号：US20140040688A1
公开(公告)日：2014-02-06
申请号：US13682749
申请日：2012-11-21
申请人： Wanggen Zhang , Sian Lu , Shayan Zhang
发明人： Wanggen Zhang , Sian Lu , Shayan Zhang
IPC分类号： G01R31/3177
CPC分类号： G01R31/318541
摘要： A low power scan flip-flop cell includes a multiplexer, a master latch, a scan slave latch and a data slave latch. The master latch is connected to the multiplexer, and used for generating a first latch signal. The scan slave latch is connected to the master latch, and generates a scan output (SO) signal. The data slave latch is connected to the master latch, and generates a Q output depending on a scan enable (SE) input signal and the first latch signal. The Q output is maintained at a predetermined level during scan mode, which eliminates unnecessary switching of combinational logic connected to the scan flip-flop cell and thus reduces power consumption.
摘要翻译：低功率扫描触发器单元包括多路复用器，主锁存器，扫描从锁存器和数据从锁存器。主锁存器连接到多路复用器，用于产生第一个锁存信号。扫描从锁存器连接到主锁存器，并产生扫描输出（SO）信号。数据从锁存器连接到主锁存器，并根据扫描使能（SE）输入信号和第一锁存信号产生Q输出。在扫描模式期间，Q输出保持在预定电平，这消除了连接到扫描触发器单元的组合逻辑的不必要的切换，从而降低功耗。

7. 发明申请

US20130300497A1 RECONFIGURABLE INTEGRATED CIRCUIT 有权
标题翻译：可重构集成电路
公开(公告)号：US20130300497A1
公开(公告)日：2013-11-14
申请号：US13609283
申请日：2012-09-11
申请人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
发明人： Xu Zhang , Chad J. Lerma , Kai Liu , Sian Lu , Hao Wang , Shayan Zhang , Wanggen Zhang
IPC分类号： H01L25/00
CPC分类号： H03K19/177 , H01L2224/48137 , H01L2224/49171 , H03K19/17744
摘要： A reconfigurable integrated circuit (IC) has IC interface terminals including circuit input terminals and circuit output terminals. A bypass controller and bypass circuitry are coupled to each other, and to at least one of the circuit input terminals and at least one of the circuit output terminals. A processing circuit has multiple circuit modules coupled to the bypass circuitry. The processing circuit is coupled to at least one of the circuit input terminals and at least one of the circuit output terminals. In operation the bypass controller controls the bypass circuitry to selectively couple at least one pair of the IC interface terminals together, the pair including one of the circuit input terminals and one of the circuit output terminals. When the pair of IC interface terminals are coupled together, at least one of the circuit modules is selectively de-coupled from the pair of the IC terminals.
摘要翻译：可重构集成电路（IC）具有包括电路输入端子和电路输出端子的IC接口端子。旁路控制器和旁路电路彼此耦合，并且耦合到至少一个电路输入端子和至少一个电路输出端子。处理电路具有耦合到旁路电路的多个电路模块。处理电路耦合到至少一个电路输入端和至少一个电路输出端。在操作中，旁路控制器控制旁路电路以选择性地将至少一对IC接口端子耦合在一起，该对包括电路输入端子之一和电路输出端子之一。当一对IC接口端子耦合在一起时，至少一个电路模块被选择性地从一对IC端子去耦合。

8. 发明授权

US08004907B2 SRAM with read and write assist 有权
标题翻译： SRAM具有读写辅助功能
公开(公告)号：US08004907B2
公开(公告)日：2011-08-23
申请号：US12479088
申请日：2009-06-05
申请人： Andrew C. Russell , Troy L. Cooper , Prashant U. Kenkare , Shayan Zhang
发明人： Andrew C. Russell , Troy L. Cooper , Prashant U. Kenkare , Shayan Zhang
IPC分类号： G11C11/00
CPC分类号： G11C11/413
摘要： A memory includes an SRAM bitcell including a pair of cross-coupled inverters, wherein a first inverter of the pair includes a first device having a body and a second inverter of the pair includes a second device having a body. A first selection circuit has a first input coupled to a first supply voltage terminal, a second input coupled to a second supply voltage terminal, and an output coupled to a first current electrode of the first device and to a first current electrode of the second device. A second selection circuit has a first input coupled to the first supply voltage terminal, a second input coupled to the second supply voltage terminal, and an output coupled to the body of each of the first and second devices. A word line coupled to the SRAM bitcell is driven by a word line driver coupled to the first supply voltage terminal.
摘要翻译：存储器包括包括一对交叉耦合的反相器的SRAM位单元，其中该对的第一反相器包括具有本体的第一器件和该对的第二反相器，其包括具有主体的第二器件。第一选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一器件的第一电流电极和第二器件的第一电流电极的输出端。第二选择电路具有耦合到第一电源电压端子的第一输入端，耦合到第二电源电压端子的第二输入端和耦合到第一和第二设备中的每一个的主体的输出端。耦合到SRAM位单元的字线由耦合到第一电源电压端子的字线驱动器驱动。

9. 发明授权

US07903483B2 Integrated circuit having memory with configurable read/write operations and method therefor 有权
标题翻译：具有可配置读/写操作的存储器的集成电路及其方法
公开(公告)号：US07903483B2
公开(公告)日：2011-03-08
申请号：US12275622
申请日：2008-11-21
申请人： Andrew C. Russell , Shayan Zhang
发明人： Andrew C. Russell , Shayan Zhang
IPC分类号： G11C29/00
CPC分类号： G11C7/1015 , G11C5/147 , G11C11/419 , G11C2207/2254
摘要： An integrated circuit having a memory and a method for operating the memory are provided. The method for operating the memory comprises: accessing a first portion of the memory, the first portion having a first access margin; detecting an error in the first portion of the memory; changing the first access margin to a second access margin, the second access margin being different than the first access margin; determining that the error is corrected with the first portion having the second access margin; and storing an access assist bit in a first storage element, the access assist bit corresponding to the first portion, wherein the assist bit, when set, indicates that subsequent accesses to the first portion are accomplished at the second access margin.
摘要翻译：提供了具有存储器的集成电路和用于操作存储器的方法。用于操作存储器的方法包括：访问存储器的第一部分，第一部分具有第一访问余量; 检测存储器的第一部分中的错误; 将所述第一访问边缘更改为第二访问边缘，所述第二访问边距不同于所述第一访问边距; 确定所述误差由具有所述第二存取余量的所述第一部分校正; 以及将访问辅助位存储在第一存储元件中，所述访问辅助位对应于所述第一部分，其中所述辅助位在被设置时指示在所述第二访问边界处完成对所述第一部分的后续访问。

10. 发明授权

US07852692B2 Memory operation testing 有权
标题翻译：内存操作测试
公开(公告)号：US07852692B2
公开(公告)日：2010-12-14
申请号：US12164755
申请日：2008-06-30
申请人： Shayan Zhang , Jack M. Higman , Michael D. Snyder
发明人： Shayan Zhang , Jack M. Higman , Michael D. Snyder
IPC分类号： G11C29/00
CPC分类号： G11C29/02 , G11C29/026 , G11C29/028 , G11C29/50 , G11C29/50012
摘要： Test circuitry for determining whether a memory can operate at a lower operating voltage. The test circuitry includes a sense circuit having a delayed sensing characteristic as compared to other sense amplifier circuits of the memory. With this circuitry, the test circuitry can determine if the sense circuit can provide valid data under more severe sensing conditions. In one example, the sense circuit includes a delay circuit in the sense enable signal path. If sense circuit can provide data at more server operating conditions, then the memory operating voltage can be lowered.
摘要翻译：用于确定存储器是否能够在较低工作电压下工作的测试电路。测试电路包括与存储器的其它读出放大器电路相比具有延迟的感测特性的感测电路。使用该电路，测试电路可以确定感测电路是否可以在更严重的感测条件下提供有效的数据。在一个示例中，感测电路在感测使能信号路径中包括延迟电路。如果感测电路可以在更多的服务器操作条件下提供数据，则可以降低存储器工作电压。

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