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1. 发明授权

US08947942B2 Semiconductor memory chip and multi-chip package using the same 有权
标题翻译：半导体存储芯片和多芯片封装使用相同
公开(公告)号：US08947942B2
公开(公告)日：2015-02-03
申请号：US13244189
申请日：2011-09-23
申请人： Bok Rim Ko , Kwang Soon Kim
发明人： Bok Rim Ko , Kwang Soon Kim
IPC分类号： G11C7/00 , G11C7/10
CPC分类号： G11C7/1045 , G11C7/1012 , G11C7/1084 , G11C2207/105
摘要： A semiconductor memory chip includes a first pad unit configured to receive a first data and a first strobe signal, and a first selection transfer unit configured to transfer the first data and the first strobe signal to a first write path circuit in a first mode, and transfer the first data and the first strobe signal to a second write path circuit in a swap mode.
摘要翻译：半导体存储器芯片包括被配置为接收第一数据和第一选通信号的第一焊盘单元和被配置为以第一模式将第一数据和第一选通信号传送到第一写路径电路的第一选择传送单元，以及在交换模式下将第一数据和第一选通信号传送到第二写路径电路。

2. 发明授权

US08422320B2 Data strobe signal generation circuit 有权
标题翻译：数据选通信号发生电路
公开(公告)号：US08422320B2
公开(公告)日：2013-04-16
申请号：US13243110
申请日：2011-09-23
申请人： Kwang Soon Kim , Bok Rim Ko
发明人： Kwang Soon Kim , Bok Rim Ko
IPC分类号： G11C7/00
CPC分类号： G11C29/022 , G11C29/14 , G11C29/46
摘要： A data strobe signal generation circuit includes: an enable signal generation unit configured to decode a test signal and generate an enable signal; an internal clock generation unit configured to generate a rising clock signal and a falling clock signal in response to the test signal; and a data strobe signal output unit configured to selectively buffer first and second powers in response to the rising clock signal and the falling clock signal, and output a data strobe signal.
摘要翻译：数据选通信号产生电路包括：使能信号生成单元，被配置为对测试信号进行解码并产生使能信号; 内部时钟生成单元，被配置为响应于测试信号产生上升时钟信号和下降时钟信号; 以及数据选通信号输出单元，被配置为响应于上升时钟信号和下降时钟信号选择性地缓冲第一和第二功率，并且输出数据选通信号。

3. 发明授权

US08873305B2 Semiconductor memory device having data compression test circuit 有权
标题翻译：具有数据压缩测试电路的半导体存储器件
公开(公告)号：US08873305B2
公开(公告)日：2014-10-28
申请号：US13337657
申请日：2011-12-27
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G11C7/10 , G11C29/40
CPC分类号： G11C7/1057 , G06F5/14 , G11C7/1084 , G11C7/1096 , G11C29/025 , G11C29/40
摘要： A semiconductor memory device includes a data transmission unit configured to transmit first input data to only a first global line driver or to the first global line driver and a second global line driver in response to a test signal, and a transmission element configured to transmit second input data only to the second global line driver in response to the test signal.
摘要翻译：一种半导体存储器件包括：数据传输单元，被配置为响应于测试信号将仅第一全局线驱动器或第一全局线驱动器和第二全局线驱动器的第一输入数据传输，以及传输元件，响应于测试信号将数据输入到第二全局线路驱动器。

4. 发明授权

US08385145B2 Semiconductor memory apparatus 失效
标题翻译：半导体存储装置
公开(公告)号：US08385145B2
公开(公告)日：2013-02-26
申请号：US12843808
申请日：2010-07-26
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G11C29/00
CPC分类号： G11C29/48 , G11C29/1201 , G11C29/26 , G11C2029/1802 , G11C2029/2602
摘要： A semiconductor memory apparatus includes memory banks, each having sub banks. The semiconductor memory apparatus is configured to allocate same test input/output line to a certain sub bank of one memory bank and a certain sub bank of another memory bank during a multi-bit test.
摘要翻译：一种半导体存储装置，包括各自具有子存储体的存储体。半导体存储装置被配置为在多位测试期间将相同的测试输入/输出线分配给一个存储体的一个子组和另一个存储体的某个子组。

5. 发明授权

US07567117B2 Data output clock signal generating apparatus and semiconductor integrated circuit with the same 有权
标题翻译：数据输出时钟信号发生装置与半导体集成电路相同
公开(公告)号：US07567117B2
公开(公告)日：2009-07-28
申请号：US11961665
申请日：2007-12-20
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G05F1/10
CPC分类号： H03K3/35613 , H03K19/017581
摘要： A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.
摘要翻译：数据时钟控制装置包括：偏置电压发生器，被配置为接收多个测试模式信号和多个熔丝信号，并产生偏置电压以确保来自外部驱动电源的预定电位差;以及时钟信号控制器配置以接收偏置电压并缓冲外部时钟信号并输出数据输出时钟信号。

6. 发明申请

US20090059708A1 SEMICONDUCTOR INTEGRATED CIRCUIT INCLUDING BANK SELECTION CONTROL BLOCK 有权
标题翻译：半导体集成电路，包括银行选择控制块
公开(公告)号：US20090059708A1
公开(公告)日：2009-03-05
申请号：US12018766
申请日：2008-01-23
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G11C8/00
CPC分类号： G11C8/12 , G11C8/14
摘要： A semiconductor integrated circuit according to one embodiment can include an up bank block that includes a first group of banks, a down bank block that includes a second group of banks, and a bank selection control block that provides up and down bank even-numbered global line control signals, up and down bank odd-numbered global line control signals, and up and down bank SDRAM write global line control signals in response to first and second group read control signals and a bank information signal in the up bank block and the down bank block. In this case, the bank selection control block may respond to a DDR signal and an SDR signal that are provided from an MRS (Mode Register Set).
摘要翻译：根据一个实施例的半导体集成电路可以包括上行块，其包括第一组存储体，包括第二组存储体的下行块，以及提供上行和下行偶数全局的存储体选择控制块线路控制信号，上行和下行奇数全局线控制信号，以及上下行SDRAM响应于第一和第二组读控制信号写入全局线控制信号，以及向上行存储块中的存储体信息信号银行块。在这种情况下，存储体选择控制块可以响应从MRS（模式寄存器组）提供的DDR信号和SDR信号。

7. 发明授权

US08929156B2 System-in package including semiconductor memory device and method for determining input/output pins of system-in package 有权
标题翻译：包括半导体存储器件的系统化封装以及用于确定系统级封装的输入/输出引脚的方法
公开(公告)号：US08929156B2
公开(公告)日：2015-01-06
申请号：US13336933
申请日：2011-12-23
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G11C7/10 , G11C7/22 , G11C29/12
CPC分类号： G11C7/222 , G11C29/12015
摘要： A semiconductor memory device includes an internal clock generation unit configured to generate an internal clock including periodic pulses during a period of a test mode; a DQ information signal generation block configured to generate DQ information signals which are sequentially enabled, in response to the internal clock; and a data output block configured to output the DQ information signals to DQ pads during a period of the test mode.
摘要翻译：半导体存储器件包括：内部时钟生成单元，被配置为在测试模式期间产生包括周期脉冲的内部时钟; DQ信息信号生成块，被配置为响应于内部时钟产生顺序启用的DQ信息信号; 以及数据输出块，被配置为在测试模式的时段期间将DQ信息信号输出到DQ焊盘。

8. 发明授权

US07863947B2 Driving strength control circuit and data output circuit in semiconductor device 有权
标题翻译：半导体器件中的驱动强度控制电路和数据输出电路
公开(公告)号：US07863947B2
公开(公告)日：2011-01-04
申请号：US12215722
申请日：2008-06-30
申请人： Bok Rim Ko , Youk Hee Kim
发明人： Bok Rim Ko , Youk Hee Kim
IPC分类号： H03K19/003 , H03K19/08 , G11C11/4096
CPC分类号： H03K19/018585
摘要： A driving strength control circuit and a data output circuit for controlling driving strength of a data driver based on a user's demand are provided to make it possible to control the driving strength through a fuse cutting. The driving strength control circuit includes a fuse signal generating unit for generating a fuse signal based on a fuse cutting, a select signal generating unit for generating select signals in response to the fuse signal, a driving control signal generating unit for receiving set-up signals and generate driving control signals in response to the select signals, and a driving signal generating unit for driving signals by decoding the driving control signals.
摘要翻译：提供了驱动强度控制电路和数据输出电路，用于根据用户的要求来控制数据驱动器的驱动强度，以便通过熔丝切割来控制驱动强度。驱动强度控制电路包括用于根据熔丝切断产生熔丝信号的熔丝信号产生单元，用于响应于熔丝信号产生选择信号的选择信号产生单元，用于接收建立信号的驱动控制信号产生单元并且响应于选择信号产生驱动控制信号;以及驱动信号产生单元，用于通过解码驱动控制信号来驱动信号。

9. 发明授权

US07826303B2 Data output circuit having shared data output control unit 有权
标题翻译：数据输出电路具有共享数据输出控制单元
公开(公告)号：US07826303B2
公开(公告)日：2010-11-02
申请号：US12156888
申请日：2008-06-05
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G11C8/00
CPC分类号： G11C7/1039 , G11C7/1051 , G11C7/1057 , G11C7/1066
摘要： A data output circuit is provided which is capable of reducing a size and current consumption by commonly using a data output control unit for a plurality of data output units. The data output circuit includes a data output control unit for receiving an external clock signal and generate clock pulses having a pulse width, a first data output unit for outputting first data in synchronization with the clock pulse, and a second data output unit for outputting second data in synchronization with the clock pulses.
摘要翻译：提供一种数据输出电路，其能够通过共同使用用于多个数据输出单元的数据输出控制单元来减小尺寸和电流消耗。数据输出电路包括用于接收外部时钟信号并产生具有脉冲宽度的时钟脉冲的数据输出控制单元，用于与时钟脉冲同步地输出第一数据的第一数据输出单元和用于输出第二数据的第二数据输出单元数据与时钟脉冲同步。

10. 发明申请

US20090261889A1 DATA OUTPUT CLOCK SIGNAL GENERATING APPARATUS AND SEMICONDUCTOR INTEGRATED CIRCUIT WITH THE SAME 有权
公开(公告)号：US20090261889A1
公开(公告)日：2009-10-22
申请号：US12496322
申请日：2009-07-01
申请人： Bok Rim Ko
发明人： Bok Rim Ko
IPC分类号： G05F1/10
CPC分类号： H03K3/35613 , H03K19/017581
摘要： A data clock control apparatus includes a bias voltage generator configured to receive a plurality of test mode signals and a plurality of fuse signals and to generate a bias voltage to secure a predetermined potential difference from an external driving power supply, and a clock signal controller configured to receive the bias voltage and to buffer an external clock signal and outputs a data output clock signal.

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