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1. 发明授权

US09318181B2 Magnetic memory devices including shared lines 有权
标题翻译：包括共享线路的磁存储器件
公开(公告)号：US09318181B2
公开(公告)日：2016-04-19
申请号：US14448717
申请日：2014-07-31
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Kee-Moon Chun , Hee-Seog Jeon
IPC分类号： G11C11/00 , G11C11/16
CPC分类号： G11C11/1675 , G11C11/16 , G11C11/1659
摘要： A magnetic memory device includes word lines, bit lines intersecting the word lines, magnetic memory elements disposed at intersections between the word lines and the bit lines, and selection transistors connected to the word lines. The magnetic memory elements share a word line among the plurality of word lines and also share a selection transistor connected to the word line that is shared among the selection transistors. Related systems and operating methods are also described.
摘要翻译：磁存储装置包括字线，与字线交叉的位线，设置在字线和位线之间的交叉处的磁存储元件，以及连接到字线的选择晶体管。磁存储元件在多个字线之间共享字线，并且共享连接到在选择晶体管之间共享的字线的选择晶体管。还描述了相关系统和操作方法。

2. 发明申请

US20150179244A1 Magnetic Memory Devices Including Magnetic Memory Cells Having Opposite Magnetization Directions 有权
标题翻译：包括具有相反磁化方向的磁记忆体的磁存储器件
公开(公告)号：US20150179244A1
公开(公告)日：2015-06-25
申请号：US14509756
申请日：2014-10-08
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
摘要翻译：磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。还讨论了相关的操作方法。

3. 发明授权

US09330745B2 Magnetic memory devices including magnetic memory cells having opposite magnetization directions 有权
标题翻译：磁存储器件包括具有相反磁化方向的磁存储单元
公开(公告)号：US09330745B2
公开(公告)日：2016-05-03
申请号：US14509756
申请日：2014-10-08
申请人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
发明人： Bo-Young Seo , Yong-Kyu Lee , Choong-Jae Lee , Hee-Seog Jeon
IPC分类号： G11C11/16
CPC分类号： G11C11/161 , G11C11/1655 , G11C11/1659 , G11C11/1673 , G11C11/1675
摘要： A magnetic memory device includes first and second magnetic memory cells coupled to first and second bit lines, respectively. The first and second magnetic memory cells respectively include a pinned magnetic layer, a free magnetic layer, and a tunnel insulating layer therebetween. Respective stacking orders of the pinned magnetic layer, the tunnel insulating layer, and the free magnetic layer are different in the first and second magnetic memory cells. The magnetic memory device further includes at least one transistor that is configured to couple the first and second magnetic memory cells to a common source line. Related methods of operation are also discussed.
摘要翻译：磁存储器件包括分别耦合到第一和第二位线的第一和第二磁存储器单元。第一和第二磁存储单元分别包括钉扎磁性层，自由磁性层和隧道绝缘层。固定磁性层，隧道绝缘层和自由磁性层的各个堆叠顺序在第一和第二磁性存储单元中是不同的。磁存储器件还包括至少一个晶体管，其被配置为将第一和第二磁存储器单元耦合到公共源极线。还讨论了相关的操作方法。

4. 发明申请

US20100265765A1 Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same 有权
标题翻译：减少程序干扰的非易失性半导体存储器件及其编程方法
公开(公告)号：US20100265765A1
公开(公告)日：2010-10-21
申请号：US12662431
申请日：2010-04-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
发明人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
IPC分类号： G11C16/02 , G11C16/10
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/24
摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.
摘要翻译：提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

5. 发明申请

US20060092705A1 Semiconductor device having multi-bit nonvolatile memory cell and methods of fabricating the same 有权
标题翻译：具有多位非易失性存储单元的半导体器件及其制造方法
公开(公告)号：US20060092705A1
公开(公告)日：2006-05-04
申请号：US11256554
申请日：2005-10-21
申请人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Sung-Taeg Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/0475 , G11C11/5621 , G11C11/5692 , G11C16/0458 , H01L27/115 , H01L27/11521 , H01L27/11524 , H01L27/11568
摘要： A semiconductor device having a multi-bit nonvolatile memory cell is provided. The semiconductor device comprises a multi-bit nonvolatile memory unit cell sharing a source and a drain region and having a plurality of transistors. The plurality of transistors each comprise at least one control gate and at least one charge storage region. The charge storage regions are for accumulating charges within each of the plurality of transistors of the memory unit cell. Each of the control gates are connected to at least one control voltage to shift a threshold voltage in each of the plurality of transistors for storing multi-bit per unit cell.
摘要翻译：提供具有多位非易失性存储单元的半导体器件。半导体器件包括共享源极和漏极区域并具有多个晶体管的多位非易失性存储单元单元。多个晶体管每个包括至少一个控制栅极和至少一个电荷存储区域。电荷存储区域用于在存储单元的多个晶体管的每一个内累积电荷。每个控制栅极被连接到至少一个控制电压以移位多个晶体管中的每个晶体管中的阈值电压以存储每位单元的多位。

6. 发明授权

US07553725B2 Nonvolatile memory devices and methods of fabricating the same 失效
标题翻译：非易失性存储器件及其制造方法
公开(公告)号：US07553725B2
公开(公告)日：2009-06-30
申请号：US11488911
申请日：2006-07-18
申请人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
发明人： Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Sung-Taeg Kang , Bo-Young Seo , Hyok-Ki Kwon
IPC分类号： H01L21/336
CPC分类号： H01L27/11524 , G11C16/0433 , H01L21/28273 , H01L27/115 , H01L27/11521 , H01L29/66825
摘要： A nonvolatile memory cell includes a source region and a drain region which are disposed in a semiconductor substrate and spaced apart from each other, a source selection line and a drain selection line disposed over the semiconductor substrate between the source region and the drain region. The source selection line and the drain selection line are disposed adjacent to the source region and the drain region, respectively. The nonvolatile memory cell further includes a cell gate pattern disposed over the semiconductor substrate between the source selection line and the drain selection line, a first floating impurity region provided in the semiconductor substrate under a gap region between the source selection line and the cell gate pattern and a second floating impurity region provided in the semiconductor substrate under a gap region between the drain selection line and the cell gate pattern. Distances between the cell gate pattern and the selection lines are less than widths of the selection lines.
摘要翻译：非易失性存储单元包括设置在半导体衬底中并彼此间隔开的源极区和漏极区，设置在源极区和漏极区之间的半导体衬底上的源极选择线和漏极选择线。源极选择线和漏极选择线分别设置在源极区域和漏极区域附近。非易失性存储单元还包括设置在源极选择线和漏极选择线之间的半导体衬底之上的单元栅极图案，设置在源极选择线和单元栅极图案之间的间隙区域的半导体衬底中的第一浮动杂质区域以及在所述漏极选择线和所述单元栅极图案之间的间隙区域处设置在所述半导体衬底中的第二浮置杂质区域。单元栅极图案和选择线之间的距离小于选择线的宽度。

7. 发明申请

US20070195595A1 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US20070195595A1
公开(公告)日：2007-08-23
申请号：US11600427
申请日：2006-11-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
IPC分类号： G11C16/04
CPC分类号： G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.
摘要翻译：非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

8. 发明授权

US07515468B2 Nonvolatile memory device 有权
标题翻译：非易失性存储器件
公开(公告)号：US07515468B2
公开(公告)日：2009-04-07
申请号：US11600427
申请日：2006-11-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
发明人： Bo-Young Seo , Hee-Seog Jeon , Jeong-Uk Han , Sung-Taeg Kang
IPC分类号： G11C11/34
CPC分类号： G11C16/0408 , H01L27/115 , H01L27/11521 , H01L27/11524
摘要： A nonvolatile memory device includes a memory cell unit including a pair of memory transistors and one select transistor. The select transistor is disposed between the pair of memory transistors formed in an active region in a semiconductor substrate. Two bit lines are provided, one bit line being connected to a corresponding one of the pair of memory transistors, and the other bit line being connected to a corresponding other of the pair of memory transistors.
摘要翻译：非易失性存储器件包括具有一对存储晶体管和一个选择晶体管的存储单元单元。选择晶体管设置在形成在半导体衬底中的有源区中的一对存储晶体管之间。提供了两个位线，一个位线连接到该对存储晶体管中对应的一个位线，另一个位线连接到该对存储晶体管中的相应另一个。

9. 发明授权

US08111553B2 Non-volatile semiconductor memory device in which program disturb is reduced and method of programming the same 有权
标题翻译：减少程序干扰的非易失性半导体存储器件及其编程方法
公开(公告)号：US08111553B2
公开(公告)日：2012-02-07
申请号：US12662431
申请日：2010-04-16
申请人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
发明人： Bo-Young Seo , Hee-Seog Jeon , Kwang-Tae Kim , Ji-Hoon Park , Myung-Jo Chun
IPC分类号： G11C11/34 , G11C16/06
CPC分类号： G11C16/10 , G11C16/0433 , G11C16/24
摘要： A non-volatile semiconductor memory device capable of reducing program disturb and a method of programming the same are provided. A bit line connected to a non-selected memory cell in the same block as a selected memory cell enters a floating state by inactivating a bit line selection switch, so that voltage levels of an first conductivity type channel and a source/drain terminal formed in a pocket second conductivity type well below a memory transistor have an intermediate level of a voltage level of a selection line and the pocket P type well. Therefore, program disturb caused by FN tunneling and junction hot electrons can be inhibited.
摘要翻译：提供了能够减少编程干扰的非易失性半导体存储器件及其编程方法。连接到与选择的存储单元相同的块中的未选择的存储单元的位线通过使位线选择开关失活而进入浮置状态，使得形成在第一导电类型沟道和源极/漏极端子中的电压电平在存储晶体管之下的凹穴第二导电类型具有选择线的电压电平的中间电平和口袋P型。因此，可以抑制由FN隧穿和结热电子引起的程序干扰。

10. 发明申请

US20080130367A1 Byte-Erasable Nonvolatile Memory Devices 审中-公开
标题翻译：字节可擦除非易失性存储器件
公开(公告)号：US20080130367A1
公开(公告)日：2008-06-05
申请号：US12027735
申请日：2008-02-07
申请人： Sung-Taeg Kang , Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Bo-Young Seo , Chang-Min Jeon , Eun-Mi Hong
发明人： Sung-Taeg Kang , Hee-Seog Jeon , Jeong-Uk Han , Chang-Hun Lee , Bo-Young Seo , Chang-Min Jeon , Eun-Mi Hong
IPC分类号： G11C16/14
CPC分类号： G11C7/18 , G11C16/16 , H01L27/115 , H01L27/11521
摘要： A nonvolatile memory device includes a semiconductor well region of first conductivity type on a semiconductor substrate and a common source diffusion region of second conductivity type extending in the semiconductor well region and forming a P-N rectifying junction therewith. A byte-erasable EEPROM memory array is provided in the semiconductor well region. This byte-erasable EEPROM memory array is configured to support independent erasure of first and second pluralities of EEPROM memory cells therein that are electrically connected to the common source diffusion region.
摘要翻译：非易失性存储器件包括半导体衬底上的第一导电类型的半导体阱区域和在半导体阱区域中延伸的第二导电类型的公共源极扩散区域，并与其形成P-N整流结。在半导体阱区域中提供一个字节可擦除EEPROM存储器阵列。该字节可擦除EEPROM存储器阵列被配置为支持其中与公共源扩散区电连接的第一和第二多个EEPROM存储器单元的独立擦除。

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