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1. 发明授权

US5801083A Use of polymer spacers for the fabrication of shallow trench isolation regions with rounded top corners 失效
标题翻译：使用聚合物间隔件制造具有圆角顶角的浅沟槽隔离区域
公开(公告)号：US5801083A
公开(公告)日：1998-09-01
申请号：US954046
申请日：1997-10-20
申请人： Bo Yu , Qing Hua Zhong , Jian Hui Ye , Mei Sheng Zhou
发明人： Bo Yu , Qing Hua Zhong , Jian Hui Ye , Mei Sheng Zhou
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76232 , Y10S148/05 , Y10S148/161 , Y10S438/978
摘要： A method for forming insulator filled, shallow trench isolation regions, with rounded corners, has been developed. The process features the use of a polymer coated opening, in an insulator layer, used as a mask to define the shallow trench region in silicon. After completion of the shallow trench formation the polymer spacers are removed, exposing a region of unetched semiconductor, that had been protected by the polymer spacers, during the shallow trench dry etching procedure. The sharp corner, at the intersection between the shallow trench and the unetched region of semiconductor, is then converted to a rounded corner, via thermal oxidation of exposed silicon surfaces. The polymer spacers also eliminate the top corner wraparound.
摘要翻译：已经开发了用于形成具有圆角的绝缘体填充的浅沟槽隔离区域的方法。该方法的特征在于在绝缘体层中使用聚合物涂布的开口，用作掩模以限定硅中的浅沟槽区域。在浅沟槽形成完成之后，去除聚合物间隔物，暴露在浅沟槽干法蚀刻过程中被聚合物间隔物保护的未蚀刻半导体区域。然后，通过暴露的硅表面的热氧化，在浅沟槽和半导体的未蚀刻区域之间的交叉点处的尖角被转换成圆角。聚合物间隔物也消除了顶角环绕。

2. 发明授权

US6140206A Method to form shallow trench isolation structures 有权
标题翻译：形成浅沟槽隔离结构的方法
公开(公告)号：US6140206A
公开(公告)日：2000-10-31
申请号：US332425
申请日：1999-06-14
申请人： Jian Xun Li , Qing Hua Zhong , Mei Sheng Zhou
发明人： Jian Xun Li , Qing Hua Zhong , Mei Sheng Zhou
IPC分类号： H01L21/762 , H01L21/76
CPC分类号： H01L21/76224
摘要： A method of forming a shallow trench isolation trenches in a silicon substrate of an integrated circuit device is achieved. A silicon substrate is provided. A buffer layer is deposited overlying the silicon substrate. An etching endpoint layer is deposited overlying the buffer layer. A silicon layer is deposited layer overlying the etching endpoint layer. A photoresist layer is coated overlying the silicon layer. The photoresist layer is developed wherein the photoresist layer is removed where the trenches are planned. The silicon layer, the etching endpoint layer, and the buffer layer are etched through to expose the top surface of the silicon substrate. The silicon layer and the silicon substrate layer are etched until the top surface of the etching endpoint layer is exposed, and the trenches are thereby formed. The integrated circuit device is completed.
摘要翻译：实现了在集成电路器件的硅衬底中形成浅沟槽隔离沟槽的方法。提供硅衬底。沉积在硅衬底上的缓冲层。沉积在缓冲层上的蚀刻端点层。硅层是沉积在覆盖蚀刻终点层上的层。涂覆在硅层上的光致抗蚀剂层。显影光致抗蚀剂层，其中在规划沟槽的情况下去除光致抗蚀剂层。蚀刻硅层，蚀刻终点层和缓冲层以露出硅衬底的顶表面。蚀刻硅层和硅衬底层，直到蚀刻终点层的顶表面露出，从而形成沟槽。集成电路装置完成。

3. 发明授权

US07902066B2 Damascene contact structure for integrated circuits 有权
标题翻译：集成电路的镶嵌接触结构
公开(公告)号：US07902066B2
公开(公告)日：2011-03-08
申请号：US11535069
申请日：2006-09-26
申请人： Jian Hui Ye , Mei Sheng Zhou
发明人： Jian Hui Ye , Mei Sheng Zhou
IPC分类号： H01L21/4763
CPC分类号： H01L21/76808 , H01L21/31144 , H01L21/76846 , H01L21/76895 , H01L21/76897 , H01L23/485 , H01L23/53238
摘要： Interconnects for integrated circuits, such as damascene structures are formed using a hard mask. The hard mask is formed from, for example, high-k dielectric material such as hafnium oxide or other materials having high etch selectivity to the interconnect dielectric material. This enables a thin mask to etch vias and trenches in the interconnect dielectric layer, avoiding the problems associated with the use of thick mask layers, such as contact hole striations and small depth of focus, which can result in shorts or opens.
摘要翻译：集成电路的互连（如镶嵌结构）使用硬掩模形成。硬掩模由例如高k电介质材料形成，例如氧化铪或对互连电介质材料具有高蚀刻选择性的其它材料。这使得薄掩模能够蚀刻互连电介质层中的通孔和沟槽，从而避免与使用厚掩模层（例如接触孔条纹和小焦点深度）相关联的问题，这可能导致短路或打开。

4. 发明授权

US08394724B2 Processing with reduced line end shortening ratio 有权
标题翻译：处理缩短了线端缩短率
公开(公告)号：US08394724B2
公开(公告)日：2013-03-12
申请号：US11843629
申请日：2007-08-22
申请人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
发明人： Hai Cong , Wei Loong Loh , Krishan Gopal , Xin Zhang , Mei Sheng Zhou , Pradeep Ramachandramurthy Yelehanka
IPC分类号： H01L21/312
CPC分类号： H01L21/32137 , H01L21/32139
摘要： A method for forming device features with reduced line end shortening (LES) includes trimming the device feature to achieve the desired sub-ground rule critical dimension during the etch to form the device feature.
摘要翻译：用于形成具有减少的线端缩短（LES）的器件特征的方法包括修整器件特征以在蚀刻期间实现期望的子接地规则临界尺寸以形成器件特征。

5. 发明授权

US08324011B2 Implementation of temperature-dependent phase switch layer for improved temperature uniformity during annealing 有权
标题翻译：实现温度相关的开关层，以提高退火过程中的温度均匀性
公开(公告)号：US08324011B2
公开(公告)日：2012-12-04
申请号：US11853156
申请日：2007-09-11
申请人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
发明人： Chyiu Hyia Poon , Alex See , Mei Sheng Zhou
IPC分类号： H01L21/00
CPC分类号： H01L21/324 , H01L21/268
摘要： The present invention provides a method of annealing a semiconductor by applying a temperature-dependant phase switch layer to a semiconductor structure. The temperature-dependant phase switch layer changes phase from amorphous to crystalline at a predetermined temperature. When the semiconductor structure is annealed, electromagnetic radiation passes through the temperature-dependant phase switch layer before reaching the semiconductor structure. When a desired annealing temperature is reached the temperature-dependant phase switch layer substantially blocks the electromagnetic radiation from reaching the semiconductor structure. As a result, the semiconductor is annealed at a consistent temperature across the wafer. The temperature at which the temperature-dependant phase switch layer changes phase can be controlled by an ion implantation process.
摘要翻译：本发明提供了一种通过向半导体结构施加温度相关的相位开关层来退火半导体的方法。温度相关的相位开关层在预定温度下将相从非晶形变化为结晶。当半导体结构退火时，电磁辐射在到达半导体结构之前通过温度相关的相位开关层。当达到期望的退火温度时，温度相关的相位开关层基本上阻止电磁辐射到达半导体结构。结果，半导体在晶片上以一致的温度退火。温度相关的相位开关层改变相位的温度可以通过离子注入工艺来控制。

6. 发明申请

US20110281410A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME 有权
标题翻译：用于制造具有外延通道的半导体器件和具有其的晶体管的方法
公开(公告)号：US20110281410A1
公开(公告)日：2011-11-17
申请号：US13190805
申请日：2011-07-26
申请人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
发明人： JINPING LIU , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/8238 , H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

7. 发明授权

US08012839B2 Method for fabricating a semiconductor device having an epitaxial channel and transistor having same 有权
标题翻译：用于制造具有外延沟道的半导体器件的方法和具有其的晶体管
公开(公告)号：US08012839B2
公开(公告)日：2011-09-06
申请号：US12040562
申请日：2008-02-29
申请人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/336
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

8. 发明授权

US07966142B2 Multi-variable regression for metrology 有权
标题翻译：计量学的多元回归
公开(公告)号：US07966142B2
公开(公告)日：2011-06-21
申请号：US12103690
申请日：2008-04-15
申请人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
发明人： Wen Zhan Zhou , Zheng Zou , Jasper Goh , Mei Sheng Zhou
IPC分类号： G01D21/00 , G06F19/00
CPC分类号： H01L22/12 , G01B21/045 , G01B2210/56 , H01L22/20
摘要： A method for assessing metrology tool accuracy is described. Multi-variable regression is used to define the accuracy of a metrology tool such that the interaction between different measurement parameters is taken into account. A metrology tool under test (MTUT) and a reference metrology tool (RMT) are used to measure a set of test profiles. The MTUT measures the test profiles to generate a MTUT data set for a first measurement parameter. The RMT measures the test profiles to generate RMT data sets for the first measurement parameter, and at least a second measurement parameter. Multi-variable regression is then performed to generate a best-fit plane for the data sets. The coefficient of determination (R2 value) represents the accuracy index of the MTUT.
摘要翻译：描述了一种评估测量工具精度的方法。多变量回归用于定义计量工具的准确性，以便考虑不同测量参数之间的相互作用。被测量的测量工具（MTUT）和参考计量工具（RMT）用于测量一组测试曲线。 MTUT测量测试配置文件，以生成第一个测量参数的MTUT数据集。 RMT测量测试配置文件以生成用于第一测量参数的RMT数据集和至少第二测量参数。然后执行多变量回归以为数据集生成最佳拟合平面。测定系数（R2值）表示MTUT的精度指标。

9. 发明授权

US07776699B2 Strained channel transistor structure and method 有权
标题翻译：应变通道晶体管结构和方法
公开(公告)号：US07776699B2
公开(公告)日：2010-08-17
申请号：US12025788
申请日：2008-02-05
申请人： Jin Ping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jin Ping Liu , Alex K H See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L29/778
CPC分类号： H01L29/7848 , H01L21/26506 , H01L29/165 , H01L29/66636
摘要： A transistor device structure comprising: a substrate portion formed from a first material; and a source region, a drain region and a channel region formed in said substrate, the source and drain regions comprising a plurality of islands of a second material different from the first material, the islands being arranged to induce a strain in said channel region of the substrate.
摘要翻译：一种晶体管器件结构，包括：由第一材料形成的衬底部分; 以及源区域，漏极区域和形成在所述衬底中的沟道区域，所述源极和漏极区域包括与所述第一材料不同的多个第二材料岛，所述岛被布置成在所述沟道区域中引起应变底物。

10. 发明申请

US20090218597A1 METHOD FOR FABRICATING A SEMICONDUCTOR DEVICE HAVING AN EPITAXIAL CHANNEL AND TRANSISTOR HAVING SAME 有权
标题翻译：用于制造具有外延通道的半导体器件和具有其的晶体管的方法
公开(公告)号：US20090218597A1
公开(公告)日：2009-09-03
申请号：US12040562
申请日：2008-02-29
申请人： Jinping Liu , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
发明人： Jinping Liu , Alex KH See , Mei Sheng Zhou , Liang Choo Hsia
IPC分类号： H01L21/336 , H01L29/78
CPC分类号： H01L29/66636 , H01L21/823807 , H01L29/1054 , H01L29/165 , H01L29/4958 , H01L29/4975 , H01L29/51 , H01L29/66545 , H01L29/66651 , H01L29/7848
摘要： A transistor having an epitaxial channel and a method for fabricating a semiconductor device having an epitaxial channel, the method including forming a hardmask on a substrate and forming an opening in the hardmask. The opening is geometrically characterized by a long dimension and a short dimension, and the opening is arranged in a predetermined manner relative to the channel region of a transistor. An epitaxial material is formed in the opening that induces strain in substrate regions proximate to the epitaxial material. The epitaxial material is confined to the opening, such that an epitaxial channel is formed. A transistor is fabricated in proximity to the epitaxial channel, such that the strain induced in the substrate provides enhanced transistor performance. By confining the epitaxial material to a predefined channel in the substrate, plastic strain relaxation of the epitaxial material is minimized and a maximum amount of strain is induced in the substrate.
摘要翻译：具有外延沟道的晶体管和用于制造具有外延沟道的半导体器件的方法，所述方法包括在衬底上形成硬掩模并在硬掩模中形成开口。开口的几何特征在于长尺寸和短尺寸，并且开口以相对于晶体管的沟道区域的预定方式布置。在开口中形成外延材料，其在靠近外延材料的衬底区域中引起应变。外延材料限于开口，从而形成外延沟道。在外延沟道附近制造晶体管，使得在衬底中感应的应变提供增强的晶体管性能。通过将外延材料限制在衬底中的预定通道，外延材料的塑性应变弛豫被最小化，并且在衬底中引起最大量的应变。

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