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1. 发明授权

US07358104B2 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US07358104B2
公开(公告)日：2008-04-15
申请号：US11359138
申请日：2006-02-22
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L21/00
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L27/1244 , H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

2. 发明申请

US20060138424A1 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US20060138424A1
公开(公告)日：2006-06-29
申请号：US11359138
申请日：2006-02-22
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L27/1244 , H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mas, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the firs wire via the contact holes.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔使用感光膜作为蚀刻的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界，并且形成通过接触孔连接到第一线的第二线。

3. 发明授权

US07061015B2 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US07061015B2
公开(公告)日：2006-06-13
申请号：US10466299
申请日：2002-10-08
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136227 , G02F1/136286 , H01L21/76802 , H01L21/76804 , H01L23/53295 , H01L27/12 , H01L27/1244 , H01L27/1248 , H01L2924/0002 , H01L2924/00
摘要： A gate wire is formed on a substrate. Next, after forming a gate insulating film, a semiconductor layer and an ohmic contact layer subsequently are formed thereon. Next, a data wire is formed. Next, a passivation layer and an organic insulating film are deposited, and patterned to form contact holes for exposing the drain electrode, the gate pad and the data pad, respectively. Here, the organic insulating film around the contact holes is formed thinner than that in the other portions. Next, the organic insulating film around the contact holes is removed by an ashing process to expose the borderline of the passivation layer in the contact holes, thereby removing an under-cut. Then, a pixel electrode, an assistant gate pad and an assistant data pad respectively connected to the drain electrode, the gate pad and the data pad are formed.
摘要翻译：在基板上形成栅极线。接下来，在形成栅极绝缘膜之后，随后形成半导体层和欧姆接触层。接下来，形成数据线。接下来，沉积钝化层和有机绝缘膜，并图案化以形成用于分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。这里，接触孔周围的有机绝缘膜的厚度比其他部分薄。接下来，通过灰化处理去除接触孔周围的有机绝缘膜，以暴露接触孔中的钝化层的边界线，从而去除下切。然后，形成分别连接到漏电极，栅极焊盘和数据焊盘的像素电极，辅助栅极焊盘和辅助数据焊盘。

4. 发明授权

US07737445B2 Contact portion of semiconductor device, and thin film transistor array panel for display device including the contact portion 有权
标题翻译：半导体器件的接触部分和包括该接触部分的显示器件的薄膜晶体管阵列面板
公开(公告)号：US07737445B2
公开(公告)日：2010-06-15
申请号：US12030992
申请日：2008-02-14
申请人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
发明人： Bo Sung Kim , Kwan-Wook Jung , Wan-Shick Hong , Sang-Gab Kim , Mun-Pyo Hong
IPC分类号： H01L29/04
CPC分类号： G02F1/13458 , G02F1/136286 , G02F2001/136295 , H01L27/124 , H01L27/1244 , H01L27/1248 , H01L27/1288
摘要： A method for manufacturing a semiconductor device including forming a first wire on a substrate, forming a lower film on the first wire, forming a photosensitive pattern on the lower film using a photosensitive material, forming contact holes for exposing the first wire by etching the lower film using the photosensitive film as an etching mask, removing part of the photosensitive film pattern by an ashing process to expose a borderline of the lower film defining the contact holes and forming second wire connected to the first wire via the contact holes.
摘要翻译：一种制造半导体器件的方法，包括在衬底上形成第一线，在第一线上形成下膜，使用感光材料在下膜上形成感光图案，形成用于通过蚀刻下部的第一线露出的接触孔使用感光膜作为蚀刻掩模的膜，通过灰化处理去除部分感光膜图案以暴露限定接触孔的下膜的边界线，并且经由接触孔形成连接到第一线的第二线。

5. 发明授权

US07095460B2 Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same 有权
公开(公告)号：US07095460B2
公开(公告)日：2006-08-22
申请号：US10083261
申请日：2002-02-25
申请人： Joon-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
发明人： Joon-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
IPC分类号： G02F1/136
CPC分类号： H01L29/66765 , G02F1/136227 , G02F2001/133357 , G02F2001/136236 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

6. 发明授权

US07615783B2 Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same 有权
公开(公告)号：US07615783B2
公开(公告)日：2009-11-10
申请号：US11436073
申请日：2006-05-17
申请人： Joon-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
发明人： Joon-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
IPC分类号： H01L51/30
CPC分类号： H01L29/66765 , G02F1/136227 , G02F2001/133357 , G02F2001/136236 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

7. 发明申请

US20060209223A1 Thin film transistor array substrate using low dielectric insulating layer and method of fabricating the same 有权
公开(公告)号：US20060209223A1
公开(公告)日：2006-09-21
申请号：US11436073
申请日：2006-05-17
申请人： Joo-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
发明人： Joo-Hoo Choi , Wan-Shick Hong , Dae-Jin Kwon , Kwan-Wook Jung , Sang-Gab Kim , Kyu-Ha Jung
IPC分类号： G02F1/136
CPC分类号： H01L29/66765 , G02F1/136227 , G02F2001/133357 , G02F2001/136236 , H01L27/12 , H01L29/458 , H01L29/4908
摘要： A thin film transistor array substrate is provided. The substrate includes an insulating substrate, a first signal line formed on the insulating substrate, a first insulating layer formed on the first signal line, a second signal line formed on the first insulating layer while crossing over the first signal line, a thin film transistor connected to the first and the second signal lines, a second insulating layer formed on the thin film transistor, the second insulating layer having dielectric constant about 4.0 or less, and the second insulating layer having a first contact hole exposing a predetermined electrode of the thin film transistor, and a first pixel electrode formed on the second insulating layer while being connected to the predetermined electrode of the thin film transistor through the first contact hole.

8. 发明申请

US20050173732A1 Wire for a display device, a method for manufacturing the same, a thin film transistor array panel including the wire, and a method for manufacturing the same 失效
标题翻译：用于显示装置的线，其制造方法，包括该线的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US20050173732A1
公开(公告)日：2005-08-11
申请号：US10501597
申请日：2002-07-29
申请人： Seung-Hee Yu , Mun-Pyo Hong , Soo-Guy Rho , Nam-Seok Rho , Keun-Kyu Song , Hee-Hwan Choe , Bo-Sung Kim , Sang-Gab Kim , Sung-Chul Kang , Hong-Sick Park
发明人： Seung-Hee Yu , Mun-Pyo Hong , Soo-Guy Rho , Nam-Seok Rho , Keun-Kyu Song , Hee-Hwan Choe , Bo-Sung Kim , Sang-Gab Kim , Sung-Chul Kang , Hong-Sick Park
IPC分类号： G02F1/1343 , G02F1/1362 , G02F1/1368 , G09F9/30 , H01L21/28 , H01L21/3205 , H01L23/52 , H01L29/417 , H01L29/423 , H01L29/49 , H01L29/786 , H01L27/10
CPC分类号： G02F1/136286 , G02F2001/136295
摘要： First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(N114)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and pattered to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads. A transparent conductive material or a reflective conductive material is deposited and patterned to form a plurality of pixel electrodes, a plurality of subsidiary gate pads and a plurality of subsidiary data pads electrically connected to the drain electrodes, the gate pads and the data pads, respectively. The gate lines and the data lines with low reflectance are used as a light-blocking film for blocking the light leakage between the pixel areas, and do not increase the black brightness. Accordingly, a separate black matrix need not be provided on the color filter panel, thereby securing both aperture ration of the pixel and high contrast ratio.
摘要翻译：首先，使用包括8-12％Ce（NH 4）2（NO 3）6的蚀刻剂沉积和图案化Cr膜和CrOx膜， SUB，10-20％NH 3和剩余的超纯水，以形成包括多个栅极线，多个栅电极和多个栅极焊盘的栅极线。接下来，依次形成栅极绝缘膜，半导体层和欧姆接触层。依次沉积Cr膜和CrOx膜，并使用包括8-12％Ce（N11 4）2（NO 3）3的蚀刻剂进行图案化，）6N，10-20％NH 3和剩余的超纯水，以形成数据线，其包括多条数据线，多个源电极，多个漏极电极和多个数据焊盘。钝化层被沉积并图案化以形成分别暴露漏电极，栅极焊盘和数据焊盘的多个接触孔。沉积透明导电材料或反射导电材料以形成多个像素电极，分别与漏电极，栅极焊盘和数据焊盘电连接的多个辅助栅极焊盘和多个辅助数据焊盘。栅极线和低反射率的数据线被用作阻挡像素区域之间的漏光的遮光膜，并且不增加黑色亮度。因此，不需要在滤色器面板上设置单独的黑矩阵，从而确保像素的孔径比和高对比度。

9. 发明授权

US07638800B2 Wire for a display device, a method for manufacturing the same, a thin film transistor array panel including the wire, and a method for manufacturing the same 失效
标题翻译：用于显示装置的线，其制造方法，包括该线的薄膜晶体管阵列面板及其制造方法
公开(公告)号：US07638800B2
公开(公告)日：2009-12-29
申请号：US10501597
申请日：2002-07-29
申请人： Seung-Hee Yu , Mun-Pyo Hong , Soo-Guy Rho , Nam-Seok Rho , Keun-Kyu Song , Hee-Hwan Choe , Bo-Sung Kim , Sang-Gab Kim , Sung-Chul Kang , Hong-Sick Park
发明人： Seung-Hee Yu , Mun-Pyo Hong , Soo-Guy Rho , Nam-Seok Rho , Keun-Kyu Song , Hee-Hwan Choe , Bo-Sung Kim , Sang-Gab Kim , Sung-Chul Kang , Hong-Sick Park
IPC分类号： H01L21/84
CPC分类号： G02F1/136286 , G02F2001/136295
摘要： First, a Cr film and a CrOx film are deposited and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a gate wire including a plurality of gate lines, a plurality of gate electrodes and a plurality of gate pads. Next, a gate insulating film, a semiconductor layer and an ohmic contact layer are formed in sequence. A Cr film and CrOx film are deposited in sequence and patterned using an etchant including 8-12% Ce(NH4)2(NO3)6, 10-20% NH3 and remaining ultra pure water to form a data wire including a plurality of data lines, a plurality of source electrodes, a plurality of drain electrodes and a plurality of data pads. A passivation layer is deposited and patterned to form a plurality of contact holes respectively exposing the drain electrodes, the gate pads and the data pads. A transparent conductive material or a reflective conductive material is deposited and patterned to form a plurality of pixel electrodes, a plurality of subsidiary gate pads and a plurality of subsidiary data pads electrically connected to the drain electrodes, the gate pads and the data pads, respectively. The gate lines and the data lines with low reflectance are used as a light-blocking film for blocking the light leakage between the pixel areas, and do not increase the black brightness. Accordingly, a separate black matrix need not be provided on the color filter panel, thereby securing both aperture ratio of the pixel and high contrast ratio.
摘要翻译：首先，使用包括8-12％Ce（NH 4）2（NO 3）6，10-20％NH 3和剩余的超纯水的蚀刻剂沉积和图案化Cr膜和CrOx膜，以形成包括多个栅极线，多个栅电极和多个栅极焊盘。接下来，依次形成栅极绝缘膜，半导体层和欧姆接触层。依次沉积Cr膜和CrOx膜，并使用包括8-12％Ce（NH 4）2（NO 3）6，10-20％NH 3和剩余的超纯水的蚀刻剂进行图案化以形成包括多个数据的数据线线，多个源电极，多个漏电极和多个数据焊盘。钝化层被沉积并图案化以形成分别暴露漏电极，栅极焊盘和数据焊盘的多个接触孔。沉积透明导电材料或反射导电材料以形成多个像素电极，分别与漏电极，栅极焊盘和数据焊盘电连接的多个辅助栅极焊盘和多个辅助数据焊盘。栅极线和低反射率的数据线被用作阻挡像素区域之间的漏光的遮光膜，并且不增加黑色亮度。因此，不需要在滤色器面板上设置单独的黑矩阵，从而确保像素的开口率和高对比度。

10. 发明申请

US20080293241A1 CONTACT STRUCTURES OF WIRINGS AND METHODS FOR MANUFACTURING THE SAME, AND THIN FILM TRANSISTOR ARRAY PANELS INCLUDING THE SAME AND METHODS FOR MANUFACTURING THE SAME 审中-公开
标题翻译：接线端子结构及其制造方法，以及包括其的薄膜晶体管阵列及其制造方法
公开(公告)号：US20080293241A1
公开(公告)日：2008-11-27
申请号：US12188272
申请日：2008-08-08
申请人： Mun Pyo Hong , Sang-Gab Kim
发明人： Mun Pyo Hong , Sang-Gab Kim
IPC分类号： H01L21/44
CPC分类号： G02F1/1362 , G02F1/136286 , H01L27/124 , H01L27/1288 , H01L29/458
摘要： First, a conductive material made of aluminum-based material is deposited and patterned to form a gate wire including a gate line, a gate pad, and a gate electrode. A gate insulating layer is formed, and a semiconductor layer and an ohmic contact layer are sequentially formed. Next, a conductor layer including a lower layer of Cr and an upper layer of aluminum-based material is deposited and patterned to form a data wire include a data line intersecting the gate line, a source electrode, a drain electrode and a data pad. Then, a passivation layer is deposited and patterned to form contact holes exposing the drain electrode, the gate pad and the data pad, respectively. Next, an amorphous silicon layer is deposited, an annealing process is executed to form inter-layer reaction layers on the drain electrode, the gate pa and the data pad, which are exposed through the contact holes. Then, the amorphous silicon layer is removed. Next, IZO is deposited and patterned to form a pixel electrode, a redundant gate pad and a redundant data pad respectively and electrically connected to the drain electrode, the gate pad and the data pad via the inter-layer reaction layers.
摘要翻译：首先，将由铝基材料制成的导电材料沉积并图案化以形成包括栅极线，栅极焊盘和栅电极的栅极线。形成栅绝缘层，依次形成半导体层和欧姆接触层。接下来，沉积包括下层Cr的导体层和铝基材料的上层，并构图以形成包括与栅极线相交的数据线，源电极，漏电极和数据焊盘的数据线。然后，沉积并图案化钝化层以形成分别暴露漏电极，栅极焊盘和数据焊盘的接触孔。接下来，沉积非晶硅层，执行退火处理，以在漏电极，栅极pa和数据焊盘上形成通过接触孔露出的层间反应层。然后，去除非晶硅层。接下来，IZO被沉积和图案化以分别形成像素电极，冗余栅极焊盘和冗余数据焊盘，并经由层间反应层电连接到漏电极，栅极焊盘和数据焊盘。

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