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1. 发明申请

US20090175399A1 DIGITAL PHASE-LOCKED LOOP WITH GATED TIME-TO-DIGITAL CONVERTER 有权
标题翻译：数字锁相环与定位的时间到数字转换器
公开(公告)号：US20090175399A1
公开(公告)日：2009-07-09
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

2. 发明申请

US20090262878A1 SYSTEM AND METHOD OF CALIBRATING POWER-ON GATING WINDOW FOR A TIME-TO-DIGITAL CONVERTER (TDC) OF A DIGITAL PHASE LOCKED LOOP (DPLL) 有权
标题翻译：用于数字相位锁定（DPLL）的时间到数字转换器（TDC）的校准功率增益窗口的系统和方法
公开(公告)号：US20090262878A1
公开(公告)日：2009-10-22
申请号：US12107584
申请日：2008-04-22
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H04L7/00 , H03L7/06
CPC分类号： H03L7/085 , H03L7/18 , H03L2207/50
摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
摘要翻译：公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

3. 发明授权

US08433025B2 Digital phase-locked loop with gated time-to-digital converter 有权
标题翻译：带门控时钟数字转换器的数字锁相环
公开(公告)号：US08433025B2
公开(公告)日：2013-04-30
申请号：US11969359
申请日：2008-01-04
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/0802 , H03L7/087
摘要： A digital PLL (DPLL) includes a time-to-digital converter (TDC) and a control unit. The TDC is periodically enabled for a short duration to quantize phase information and disabled for the remaining time to reduce power consumption. The TDC receives a first clock signal and a first reference signal and provides a TDC output indicative of the phase difference between the first clock signal and the first reference signal. The control unit generates an enable signal based on a main reference signal and enables and disables the TDC with the enable signal. In one design, the control unit delays the main reference signal to obtain the first reference signal and a second reference signal, generates the enable signal based on the main reference signal and the second reference signal, and gates a main clock signal with the enable signal to obtain the first clock signal for the TDC.
摘要翻译：数字PLL（DPLL）包括时间 - 数字转换器（TDC）和控制单元。定期启用TDC以持续短时间量化相位信息，并在剩余时间内禁用TDC以降低功耗。 TDC接收第一时钟信号和第一参考信号，并提供指示第一时钟信号和第一参考信号之间的相位差的TDC输出。控制单元基于主参考信号生成使能信号，并使能和禁止具有使能信号的TDC。在一种设计中，控制单元延迟主参考信号以获得第一参考信号和第二参考信号，基于主参考信号和第二参考信号产生使能信号，并且将主时钟信号与使能信号以获得TDC的第一个时钟信号。

4. 发明授权

US08090068B2 System and method of calibrating power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL) 有权
标题翻译：用于数字锁相环（DPLL）的时间 - 数字转换器（TDC）校准电源门控窗口的系统和方法
公开(公告)号：US08090068B2
公开(公告)日：2012-01-03
申请号：US12107584
申请日：2008-04-22
申请人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
发明人： Bo Sun , Gurkanwal Singh Sahota , Zixiang Yang
IPC分类号： H03D3/24
CPC分类号： H03L7/085 , H03L7/18 , H03L2207/50
摘要： A system and method are disclosed related to calibrating a power-on gating window for a time-to-digital converter (TDC) of a digital phase locked loop (DPLL). The gating window is calibrated to ensure proper operation of the DPLL, while at the same time operating the TDC in a power efficient manner. In particular, the technique entails setting the width of the TDC gating window to a default value; operating the DPLL until the control loop is substantially locked; decreasing the width of the TDC gating window by a predetermined amount, while monitoring the phase error signal generated by the phase error device of the DPLL; determining the current width of the TDC gating window at substantially a time when the phase error arrives at or crosses a predetermined threshold; and increasing the current width of the TDC gating window by a predetermined amount to build in a margin of error for the operating width of the TDC gating window.
摘要翻译：公开了一种系统和方法，用于校准数字锁相环（DPLL）的时间 - 数字转换器（TDC）的上电门控窗口。门控窗口被校准，以确保DPLL的正常运行，同时以高效的方式操作TDC。特别地，该技术需要将TDC门控窗口的宽度设置为默认值; 操作DPLL直到控制回路基本锁定; 同时监视由DPLL的相位误差装置产生的相位误差信号，将TDC门控窗口的宽度减小预定量; 在相位误差到达或超过预定阈值的时间基本上确定TDC门控窗口的当前宽度; 并且将TDC门控窗口的当前宽度增加预定量以构成TDC门控窗口的操作宽度的误差范围。

5. 发明申请

US20090111409A1 DYNAMIC BIASING OF A VCO IN A PHASE-LOCKED LOOP 有权
标题翻译：在相位锁定环路中的VCO的动态偏移
公开(公告)号：US20090111409A1
公开(公告)日：2009-04-30
申请号：US11924318
申请日：2007-10-25
申请人： Bo Sun , Gurkanwal Singh Sahota , Yue Wu
发明人： Bo Sun , Gurkanwal Singh Sahota , Yue Wu
IPC分类号： H04B1/18
CPC分类号： H03L7/197 , H03J7/065 , H03L1/00 , H03L7/0802 , H03L7/0898 , H03L7/093 , H03L7/107 , H03L2207/06
摘要： A local oscillator includes a phase-locked loop. The phase-locked loop includes voltage controlled oscillator (VCO) and a novel VCO control circuit. The VCO control circuit may be programmable and configurable. In one example, an instruction is received onto the VCO control circuit to change the power state of the VCO. The instruction is issued by other circuitry in response to a detected change in RF channel conditions (for example, a change in a signal-to-noise determination) in a cellular telephone. In response, the VCO control circuit outputs control signals that gradually widen the loop bandwidth of the PLL, then gradually change the VCO bias current to change the VCO power state, and then narrow the loop bandwidth of the PLL back to its original bandwidth. The entire process of widening the PLL bandwidth, changing the VCO power state, and narrowing the PLL bandwidth occurs while the PLL remains locked.
摘要翻译：本地振荡器包括锁相环。锁相环包括压控振荡器（VCO）和新型VCO控制电路。 VCO控制电路可以是可编程的和可配置的。在一个示例中，在VCO控制电路上接收指令以改变VCO的功率状态。响应于在蜂窝电话中的RF信道条件（例如，信噪比确定的变化）的检测到的改变，由其他电路发出指令。作为响应，VCO控制电路输出逐渐拓宽PLL环路带宽的控制信号，然后逐渐改变VCO偏置电流，改变VCO功率状态，然后将PLL的环路带宽缩小回原来的带宽。当PLL保持锁定时，会发生整个PLL带宽扩大，改变VCO功率状态和缩小PLL带宽的过程。

6. 发明授权

US07941115B2 Mixer with high output power accuracy and low local oscillator leakage 有权
标题翻译：混频器具有高输出功率精度和低本地振荡器泄漏
公开(公告)号：US07941115B2
公开(公告)日：2011-05-10
申请号：US11855997
申请日：2007-09-14
申请人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
发明人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
IPC分类号： H04B7/00
CPC分类号： H03D7/165 , H04B1/0483 , H04B2001/0416 , H04B2001/0491
摘要： A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.
摘要翻译：电路接收第一信号（例如，基带信号）并将其与本地振荡器（LO）信号混合，并输出第二信号（例如，RFOUT信号）。该电路包括多个相同的混频器和分频器对（MFDP）电路。每个MFDP可以单独启用。每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。通过控制使能的MFDP的数量，控制第二信号的输出功率。由于MFDP都具有相同的布局，因此输出功率步长的精度提高。由于电路内的LO信号功率与启用MFDP的数量成比例地自动变化，因此避免了本地振荡器泄漏问题。

7. 发明申请

US20090302963A1 BI-POLAR MODULATOR 有权
标题翻译：双极调制器
公开(公告)号：US20090302963A1
公开(公告)日：2009-12-10
申请号：US12133726
申请日：2008-06-05
申请人： Gary John Ballantyne , Arun Jayaraman , Bo Sun , Gurkanwal Singh Sahota
发明人： Gary John Ballantyne , Arun Jayaraman , Bo Sun , Gurkanwal Singh Sahota
IPC分类号： H03C5/00
CPC分类号： H04L27/362 , H03F3/2176
摘要： A bi-polar modulator that can perform quadrature modulation using amplitude modulators is described. In one design, the bi-polar modulator includes first and second amplitude modulators and a summer. The first amplitude modulator amplitude modulates a first carrier signal with a first input signal and provides a first amplitude modulated signal. The second amplitude modulator amplitude modulates a second carrier signal with a second input signal and provides a second amplitude modulated signal. The summer sums the first and second amplitude modulated signals and provides a quadrature modulated signal that is both amplitude and phase modulated. The first and second input signals may be obtained based on absolute values of first and second modulating signals, respectively. The first and second carrier signals have phases determined based on the sign of the first and second modulating signals, respectively. Each amplitude modulator may be implemented with a class-E amplifier.
摘要翻译：描述了可以使用幅度调制器执行正交调制的双极调制器。在一种设计中，双极调制器包括第一和第二幅度调制器和夏季。第一幅度调制器利用第一输入信号调制第一载波信号并提供第一幅度调制信号。第二幅度调制器利用第二输入信号幅度调制第二载波信号，并提供第二幅度调制信号。夏季对第一和第二幅度调制信号进行求和，并提供幅度和相位调制的正交调制信号。可以分别基于第一和第二调制信号的绝对值来获得第一和第二输入信号。第一和第二载波信号分别基于第一和第二调制信号的符号确定相位。每个幅度调制器可以用E类放大器来实现。

8. 发明申请

US20090268859A1 SYSTEM AND METHOD OF CONTROLLING POWER CONSUMPTION IN A DIGITAL PHASE LOCKED LOOP (DPLL) 有权
标题翻译：在数字相位锁定环路（DPLL）中控制功耗的系统和方法
公开(公告)号：US20090268859A1
公开(公告)日：2009-10-29
申请号：US12111541
申请日：2008-04-29
申请人： Bo Sun , Gary John Ballantyne , Gurkanwal Singh Sahota
发明人： Bo Sun , Gary John Ballantyne , Gurkanwal Singh Sahota
IPC分类号： H03D3/24
CPC分类号： H03L7/00 , H03L7/0802 , H03L2207/50
摘要： An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.
摘要翻译：一种包括可编程频率装置的装置，其适于产生从一组不同频率时钟中选择的参考时钟，其中所述可编程频率装置还适于在所述不同频率之间切换时维持所述参考时钟的触发边沿的相同的时间关系时钟。该装置还包括使用所选择的参考时钟来建立输入信号和输出信号之间的预定相位关系的锁相环（PLL），例如数字PLL（DPLL）。通过在不同频率时钟之间切换时保持参考时钟的基本相同的时间关系，在改变参考时钟的同时，锁相环（PLL）的连续和有效操作不会受到明显干扰。这可以用于控制设备的功耗。

9. 发明申请

US20090075689A1 MIXER WITH HIGH OUTPUT POWER ACCURACY AND LOW LOCAL OSCILLATOR LEAKAGE 有权
标题翻译：混合器具有高输出功率精度和低的局部振荡器泄漏
公开(公告)号：US20090075689A1
公开(公告)日：2009-03-19
申请号：US11855997
申请日：2007-09-14
申请人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
发明人： Sankaran Aniruddhan , Bo Sun , Arun Jayaraman , Gurkanwal Singh Sahota
IPC分类号： H04B1/04 , H03B21/02 , H04M1/00
CPC分类号： H03D7/165 , H04B1/0483 , H04B2001/0416 , H04B2001/0491
摘要： A circuit receives a first signal (for example, a baseband signal) and mixes it with a local oscillator (LO) signal, and outputs a second signal (for example, an RFOUT signal). The circuit includes multiple identical Mixer and Frequency Divider Pair (MFDP) circuits. Each MFDP can be enabled separately. Each MFDP includes a mixer and a frequency divider that provides the mixer with a local version of the LO signal. The MFDP outputs are coupled together so that the output power of the second signal (RFOUT) is the combined output powers of the various MFDPs. By controlling the number of enabled MFDPs, the output power of the second signal is controlled. Because the MFDPs all have identical layouts, accuracy of output power step size is improved. Because LO signal power within the circuit automatically changes in proportion to the number of enabled MFDPs, local oscillator leakage problems are avoided.
摘要翻译：电路接收第一信号（例如，基带信号）并将其与本地振荡器（LO）信号混合，并输出第二信号（例如，RFOUT信号）。该电路包括多个相同的混频器和分频器对（MFDP）电路。每个MFDP可以单独启用。每个MFDP包括混频器和分频器，为混频器提供本地版本的LO信号。 MFDP输出耦合在一起，使得第二信号（RFOUT）的输出功率是各种MFDP的组合输出功率。通过控制使能的MFDP的数量，控制第二信号的输出功率。由于MFDP都具有相同的布局，因此输出功率步长的精度提高。由于电路内的LO信号功率与启用MFDP的数量成比例地自动变化，因此避免了本地振荡器泄漏问题。

10. 发明授权

US08077822B2 System and method of controlling power consumption in a digital phase locked loop (DPLL) 有权
标题翻译：在数字锁相环（DPLL）中控制功耗的系统和方法
公开(公告)号：US08077822B2
公开(公告)日：2011-12-13
申请号：US12111541
申请日：2008-04-29
申请人： Bo Sun , Gary John Ballantyne , Gurkanwal Singh Sahota
发明人： Bo Sun , Gary John Ballantyne , Gurkanwal Singh Sahota
IPC分类号： H03D3/24
CPC分类号： H03L7/00 , H03L7/0802 , H03L2207/50
摘要： An apparatus comprising a programmable frequency device adapted to generate a reference clock selected from a set of distinct frequency clocks, wherein the programmable frequency device is further adapted to maintain the same temporal relationship of the triggering edges of the reference clock when switching between the distinct frequency clocks. The apparatus further comprises a phase locked loop (PLL), such as a digital PLL (DPLL), that uses the selected reference clock to establish a predetermined phase relationship between an input signal and an output signal. By maintaining substantially the same temporal relationship of the reference clock when switching between distinct frequency clocks, the continual and effective operation of the phase locked loop (PLL) is not significantly disturbed while changing the reference clock. This may be used to control the power consumption of the apparatus.
摘要翻译：一种包括可编程频率装置的装置，其适于产生从一组不同频率时钟中选择的参考时钟，其中所述可编程频率装置还适于在所述不同频率之间切换时维持所述参考时钟的触发边沿的相同的时间关系时钟。该装置还包括使用所选择的参考时钟来建立输入信号和输出信号之间的预定相位关系的锁相环（PLL），例如数字PLL（DPLL）。通过在不同频率时钟之间切换时保持参考时钟的基本相同的时间关系，在改变参考时钟的同时，锁相环（PLL）的连续和有效操作不会受到明显干扰。这可以用于控制设备的功耗。

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