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1. 发明授权

US06510082B1 Drain side sensing scheme for virtual ground flash EPROM array with adjacent bit charge and hold 有权
标题翻译：具有相邻位充电和保持的虚拟接地闪速EPROM阵列的漏极检测方案
公开(公告)号：US06510082B1
公开(公告)日：2003-01-21
申请号：US09999869
申请日：2001-10-23
申请人： Binh Q. Le , Pau-Ling Chen , Michael A. Van Buskirk , Santosh K. Yachareni , Michael S. C. Chung , Kazuhiro Kurihara , Shane Hollmer
发明人： Binh Q. Le , Pau-Ling Chen , Michael A. Van Buskirk , Santosh K. Yachareni , Michael S. C. Chung , Kazuhiro Kurihara , Shane Hollmer
IPC分类号： G11C1604
CPC分类号： G11C16/0491 , G11C16/28
摘要： A system is disclosed for producing an indication of the logical state of a flash memory cell for virtual ground flash memory operations. The system comprises a bit line charge and hold circuit which is operable to apply a read sense voltage (e.g., about 1.2 volts) to a bit line associated with the drain terminal of a cell of the flash array adjacent to the cell which is sensed, wherein the applied drain terminal voltage is substantially the same as the cell sense voltage (e.g., about 1.2 volts) applied to the drain terminal bit line of the selected memory cell to be sensed. The system further includes a selective bit line decode circuit which is operable to select the bit lines of a memory cell to be sensed and the bit line of an adjacent cell, and a core cell sensing circuit which is operable to sense a core cell sense current at a bit line associated with a drain terminal of the selected memory cell to be sensed during memory read operations, and produce an indication of the flash memory cell logical state, which is substantially independent of charge sharing leakage current to an adjacent cell.
摘要翻译：公开了一种用于产生用于虚拟接地闪速存储器操作的闪存单元的逻辑状态的指示的系统。该系统包括位线充电和保持电路，其可操作以将读取感测电压（例如，约1.2伏特）施加到与所感测的电池相邻的闪光阵列的单元的漏极端子相关联的位线，其中所施加的漏极端子电压基本上与施加到要被感测的所选择的存储器单元的漏极端子位线的单元检测电压（例如，约1.2伏特）相同。该系统还包括选择性位线解码电路，其可操作以选择要感测的存储器单元的位线和相邻单元的位线;以及核心单元感测电路，其可操作以感测核心单元感测电流在与存储器读取操作期间被感测的所选择的存储器单元的漏极端子相关联的位线处，并产生闪存单元逻辑状态的指示，其基本上与相邻单元的电荷共享泄漏电流无关。

2. 发明授权

US06370061B1 Ceiling test mode to characterize the threshold voltage distribution of over programmed memory cells 有权
标题翻译：天花板测试模式来表征过度编程的存储单元的阈值电压分布
公开(公告)号：US06370061B1
公开(公告)日：2002-04-09
申请号：US09884583
申请日：2001-06-19
申请人： Santosh K. Yachareni , Kazuhiro Kurihara , Binh Q. Le , Michael S. C. Chung
发明人： Santosh K. Yachareni , Kazuhiro Kurihara , Binh Q. Le , Michael S. C. Chung
IPC分类号： G11C1634
CPC分类号： G11C16/3459 , G11C16/04 , G11C16/3454 , G11C16/349 , G11C29/50 , G11C29/50004
摘要： The present invention relates to flash memory systems and methods to determine the threshold voltage of core cells. In one exemplary system, there is provided a method of characterizing the high end of the threshold voltage distribution of an array of programmed cells. In accordance with the invention, an exemplary system and method are presented to apply a varying characterization signal operably through a high breakdown voltage periphery donut transistor and wordline drive transistors, which are driven into saturation by a boosted gate voltage which is higher than the applied varying characterization signal, in a manner which provides for the accurate determination of the VT of the core cells, through the comparison of the conduction in a reference cell to that of the conduction in a core cell produced by a varying characterization signal applied to the core cell gate.
摘要翻译：本发明涉及闪存系统和确定核心单元的阈值电压的方法。在一个示例性系统中，提供了表征编程单元阵列的阈值电压分布的高端的方法。根据本发明，提出了一种示例性的系统和方法，以通过高耐压周边环形晶体管和字线驱动晶体管可操作地应用变化的特征信号，该晶体管和字线驱动晶体管通过高于施加的变化的升压栅极电压而被驱动为饱和表征信号，以提供核心单元的VT的精确确定的方式，通过比较参考单元中的导通与通过施加到核心单元的变化表征信号产生的核心单元中的导通的比较门。

3. 发明授权

US06493266B1 Soft program and soft program verify of the core cells in flash memory array 有权
标题翻译：软件程序和软件程序验证闪存阵列中的核心单元
公开(公告)号：US06493266B1
公开(公告)日：2002-12-10
申请号：US09829193
申请日：2001-04-09
申请人： Santosh K. Yachareni , Darlene G. Hamilton , Binh Q. Le , Kazuhiro Kurihara
发明人： Santosh K. Yachareni , Darlene G. Hamilton , Binh Q. Le , Kazuhiro Kurihara
IPC分类号： G11C1134
CPC分类号： G11C16/3409 , G11C16/0475 , G11C16/3404 , G11C16/3436
摘要： A method and system are disclosed for memory cell soft program and soft program verify, to adjust, or correct the threshold voltage between a target minimum and maximum, which may be employed in association with a dual bit memory cell architecture. The method includes applying one reference voltage signal to the over erased core cell, and a different reference voltage signal to the reference cell, comparing the two currents produced by each, selectively verifying proper soft programming of one or more bits of the cell, determining that the dual bit memory cell is properly soft programmed. The method may also comprise selectively re-verifying proper soft programming of the cells after selectively soft programming at least one or more bits of the cell.
摘要翻译：公开了用于存储器单元软程序和软程序验证，调整或校正目标最小值与最大值之间的阈值电压的方法和系统，其可以与双位存储器单元架构相关联使用。该方法包括将一个参考电压信号施加到过擦除的核心单元，以及将不同的参考电压信号施加到参考单元，比较由每个产生的两个电流，选择性地验证单元的一个或多个位的适当的软编程，确定双位存储单元被正确软编程。该方法还可以包括在对该小区的至少一个或多个比特进行选择性软编程之后，选择性地重新验证小区的适当的软编程。

4. 发明授权

US06535424B2 Voltage boost circuit using supply voltage detection to compensate for supply voltage variations in read mode voltage 有权
标题翻译：电压升压电路使用电源电压检测来补偿读取模式电压中的电源电压变化
公开(公告)号：US06535424B2
公开(公告)日：2003-03-18
申请号：US09915018
申请日：2001-07-25
申请人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
发明人： Binh Q. Le , Masaru Yano , Santosh K. Yachareni
IPC分类号： G11C1604
CPC分类号： G11C16/08 , G11C8/08
摘要： Flash memory array systems and methods are disclosed for producing a supply regulated boost voltage, wherein the application of a supply voltage to a supply voltage level detection circuit (e.g., analog to digital converter, digital thermometer) which is used to generating one or more supply voltage level detection signals from measurement of the supply voltage level applied to the voltage boost circuit, which may be used as a boosted wordline voltage for the read mode operations of programmed memory cells, and wherein the supply voltage level detection signals are applied to a boosted voltage compensation circuit to generate one or more boosted voltage compensation signals which are applied to a voltage boost circuit operable to generate a regulated boosted voltage for a flash memory array of programmed core cells. Thus, a fast compensation means is disclosed for the VCC power supply variations typically reflected in the output of the boost voltage circuit supplied to the word line of the flash memory array, thereby generating wordline voltages during the read mode which are substantially independent of variations in the supply voltage.
摘要翻译：闪存阵列系统和方法被公开用于产生电源调节升压电压，其中将电源电压施加到用于产生一个或多个电源的电源电压电平检测电路（例如，模数转换器，数字温度计）电压电平检测信号来自测量施加到升压电路的电源电压电平，其可以用作用于编程存储器单元的读取模式操作的升压字线电压，并且其中电源电压电平检测信号被施加到升压电压补偿电路以产生一个或多个升压电压补偿信号，所述升压电压补偿信号被施加到升压电路，所述升压电路可操作以产生用于编程核心单元的闪存阵列的调节升压电压。因此，公开了一种快速补偿装置，用于通常反映在提供给闪速存储器阵列的字线的升压电压电路的输出中的VCC电源变化，从而在读取模式期间产生字线电压，其基本上与电源电压。

5. 发明授权

US06525969B1 Decoder apparatus and methods for pre-charging bit lines 有权
标题翻译：用于对位线进行预充电的解码器装置和方法
公开(公告)号：US06525969B1
公开(公告)日：2003-02-25
申请号：US09928059
申请日：2001-08-10
申请人： Kazuhiro Kurihara , Santosh K. Yachareni
发明人： Kazuhiro Kurihara , Santosh K. Yachareni
IPC分类号： G11C1606
CPC分类号： G11C16/28 , G11C7/12 , G11C16/0491 , G11C16/24 , G11C2207/063
摘要： Methods and apparatus are disclosed for reading memory cells in a virtual ground memory core, wherein a memory cell is selected to be read and an adjacent memory cell is precharged so as to mitigate leakage current associated with the adjacent cell. Decoder circuitry and methods are disclosed for selecting the memory cell to be read and the adjacent cell to be precharged, which may be used in single bit and dual bit memory devices, and which provide drain-side or source-side current sensing in the read operation.
摘要翻译：公开了用于读取虚拟地址存储器核心中的存储器单元的方法和装置，其中选择存储器单元进行读取，并且相邻存储器单元被预充电以便减轻与相邻单元相关联的泄漏电流。公开了用于选择要读取的存储器单元和要预充电的相邻单元的解码器电路和方法，其可以在单位和双位存储器件中使用，并且在读取中提供漏极侧或源极电流感测操作。

6. 发明授权

US06532175B1 Method and apparatus for soft program verification in a memory device 有权
标题翻译：用于在存储器件中进行软程序验证的方法和装置
公开(公告)号：US06532175B1
公开(公告)日：2003-03-11
申请号：US10050650
申请日：2002-01-16
申请人： Santosh K. Yachareni , Edward V. Bautista, Jr. , Weng Fook Lee
发明人： Santosh K. Yachareni , Edward V. Bautista, Jr. , Weng Fook Lee
IPC分类号： G11C1604
CPC分类号： G11C16/3409 , G11C16/3404 , G11C16/3436 , G11C16/3459
摘要： Methods and apparatus are disclosed for verifying soft programming of one or more memory cells in a memory device. The methods comprise providing a voltage source to the core cell gate, and verifying soft programming of the cell after overshoot in the regulated voltage source has settled. Also disclosed are memory devices having a logic circuit providing a regulated voltage source to the cell gate during a soft program verify operation, and a sensor to verify soft programming of the cell when a first voltage is applied to the gate from the regulated voltage source. The logic circuit provides a soft program verify signal to the sensor to verify soft programming after overshoot in the voltage source has settled.
摘要翻译：公开了用于验证存储器件中的一个或多个存储器单元的软编程的方法和装置。所述方法包括向核心单元栅极提供电压源，以及在调节电压源中的过冲后确认电池的软编程。还公开了存储器件，其具有在软程序验证操作期间向单元栅极提供调节电压源的逻辑电路，以及当从调节电压源向栅极施加第一电压时验证该单元的软编程的传感器。逻辑电路向传感器提供软程序验证信号，以验证电压源过冲后的软编程。

7. 发明授权

US06212098B1 Voltage protection of write protect cams 有权
标题翻译：写保护凸轮的电压保护
公开(公告)号：US06212098B1
公开(公告)日：2001-04-03
申请号：US09602095
申请日：2000-06-22
申请人： Santosh K. Yachareni , Edward V. Bautista, Jr.
发明人： Santosh K. Yachareni , Edward V. Bautista, Jr.
IPC分类号： G11C1604
CPC分类号： G11C16/22
摘要： The present invention discloses systems and methods for providing voltages during programming to the control gates of write protect CAMS. Upon entering a write protect CAM programming mode, at least one voltage supply circuit is activated to supply the predetermined voltage for the control gates of the write protect CAMS. When the write protect CAMS are programmed, a gate control circuit transfers a programming voltage to the control gates of the write protect CAMS. Following programming and verification of the write protect CAMS, the gate control circuit holds the control gates of the write protect CAMS at a ground voltage level.
摘要翻译：本发明公开了一种在编程期间向写保护CAMS的控制栅极提供电压的系统和方法。在进入写保护CAM编程模式时，激活至少一个电压供应电路以为写保护CAMS的控制门提供预定电压。当写保护CAMS被编程时，门控制电路将编程电压传送到写保护CAMS的控制门。在写保护CAMS的编程和验证之后，门控电路将写保护CAMS的控制栅保持在接地电压级。

8. 发明授权

US07057949B1 Method and apparatus for pre-charging negative pump MOS regulation capacitors 失效
标题翻译：负电泵MOS调节电容器预充电方法和装置
公开(公告)号：US07057949B1
公开(公告)日：2006-06-06
申请号：US10050342
申请日：2002-01-16
申请人： Feng Pan , Weng Fook Lee , Edward V. Bautista, Jr. , Santosh K. Yachareni
发明人： Feng Pan , Weng Fook Lee , Edward V. Bautista, Jr. , Santosh K. Yachareni
IPC分类号： G11C7/00
CPC分类号： G11C5/145 , G11C16/30
摘要： Methods and apparatus are disclosed for erasing a core memory cell using a negative gate voltage in a semiconductor memory device, wherein negative pump MOS regulation capacitors are pre-charged according to a pre-charge signal during a core cell erase operation. A negative voltage pump is then regulated using the pre-charged negative pump MOS regulation capacitors to provide the negative gate voltage. Apparatus is disclosed for pre-charging negative pump MOS regulation capacitors during a core cell erase operation in a memory device, which comprises a switch connected between a reference voltage and the negative pump MOS regulation capacitors, and a pre-charge control circuit providing a pre-charge signal to the switch to selectively connect the reference voltage to the negative pump MOS regulation capacitors for pre-charging thereof in an erase operation.
摘要翻译：公开了用于在半导体存储器件中使用负栅极电压擦除核心存储器单元的方法和装置，其中在核心单元擦除操作期间，根据预充电信号对负泵MOS调节电容器进行预充电。然后使用预充电的负泵MOS调节电容器调节负电压泵，以提供负栅极电压。公开了一种用于在存储器件中的核心单元擦除操作期间对负泵MOS调节电容器预充电的装置，其包括连接在参考电压和负泵MOS调节电容器之间的开关，以及提供预充电的预充电控制电路充电信号到开关，以选择性地将参考电压连接到负泵MOS调节电容器，以在擦除操作中对其进行预充电。

9. 发明授权

US06549477B1 System and method to facilitate stabilization of reference voltage signals in memory devices 失效
公开(公告)号：US06549477B1
公开(公告)日：2003-04-15
申请号：US10223486
申请日：2002-08-19
申请人： Edward V. Bautista, Jr. , Weng Fook Lee , Santosh K. Yachareni
发明人： Edward V. Bautista, Jr. , Weng Fook Lee , Santosh K. Yachareni
IPC分类号： G11C700
CPC分类号： G11C16/32 , G11C16/30
摘要： A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.

10. 发明授权

US06459628B1 System and method to facilitate stabilization of reference voltage signals in memory devices 有权
标题翻译：有助于稳定存储器件中参考电压信号的系统和方法
公开(公告)号：US06459628B1
公开(公告)日：2002-10-01
申请号：US09824166
申请日：2001-04-02
申请人： Edward V. Bautista, Jr. , Weng Fook Lee , Santosh K. Yachareni
发明人： Edward V. Bautista, Jr. , Weng Fook Lee , Santosh K. Yachareni
IPC分类号： G11C700
CPC分类号： G11C16/32 , G11C16/30
摘要： A wait system for a memory device is operative to provide a wait signal to delay performance of each operation relative the memory cell. The wait signal initially delays performance of at least one initial operation relative the memory cell during a given user mode by a first duration. After the initial wait signal, a subsequent wait signal is provided to delay performance of subsequent operations relative the memory cell during the given user mode by a second duration, which is less than the first duration.
摘要翻译：用于存储器装置的等待系统可操作以提供等待信号以相对于存储器单元延迟每个操作的性能。在给定用户模式期间，等待信号首先延迟相对于存储器单元的至少一个初始操作的性能第一持续时间。在初始等待信号之后，提供后续的等待信号以在给定的用户模式期间相对于存储器单元的后续操作的性能延迟小于第一持续时间的第二持续时间。

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