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1. 发明申请

US20060190858A1 System and method for accurately modeling an asynchronous interface using expanded logic elements 失效
标题翻译：使用扩展逻辑元素对异步接口进行精确建模的系统和方法
公开(公告)号：US20060190858A1
公开(公告)日：2006-08-24
申请号：US11054880
申请日：2005-02-10
申请人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或毛刺危险，以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

2. 发明申请

US20080040695A1 System and Method for Accurately Modeling an Asynchronous Interface using Expanded Logic Elements 有权
标题翻译：使用扩展逻辑元件精确建模异步接口的系统和方法
公开(公告)号：US20080040695A1
公开(公告)日：2008-02-14
申请号：US11874620
申请日：2007-10-18
申请人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Bing-Lun Chu , Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5031
摘要： A system and method for accurately modeling an asynchronous interface using expanded logic elements are provided. With the apparatus and method, the logic of an asynchronous interface is reduced to primitive logic elements. These primitive logic elements are expanded by the mechanisms of the present invention to take into consideration whether or not the primitive logic elements themselves may be experiencing a switching or glitch hazard and whether or not the inputs to the primitive logic elements may be based on a switching or glitch hazard from another primitive logic element in the asynchronous interface logic. These expanded logic elements are used in an integrated circuit design to replace the original primitive logic elements in the design. The asynchronous interface may then be simulated with the expanded logic elements providing outputs indicative of whether the actual data output of the expanded logic elements is deterministic or not.
摘要翻译：提供了一种使用扩展逻辑元件对异步接口进行精确建模的系统和方法。利用该装置和方法，将异步接口的逻辑简化为原始逻辑元件。这些原始逻辑元件通过本发明的机制来扩展，以考虑原语逻辑元件本身是否可能经历切换或故障危险以及基本逻辑元件的输入是否可以基于切换或异步接口逻辑中另一原始逻辑元件的故障危险。这些扩展的逻辑元件用于集成电路设计中以替代设计中的原始原始逻辑元件。然后可以用扩展的逻辑元件来模拟异步接口，该逻辑元件提供指示扩展的逻辑元件的实际数据输出是否是确定性的输出。

3. 发明申请

US20070253275A1 Clock-Gated Model Transformation for Asynchronous Testing of Logic Targeted for Free-Running, Data-Gated Logic 失效
标题翻译：用于自由运行，数据门控逻辑的逻辑异步测试的时钟门控模型转换
公开(公告)号：US20070253275A1
公开(公告)日：2007-11-01
申请号：US11380257
申请日：2006-04-26
申请人： Yee Ja , Bradley Nelson , Wolfgang Roesner
发明人： Yee Ja , Bradley Nelson , Wolfgang Roesner
IPC分类号： G11C8/00
CPC分类号： G06F17/504 , G06F17/5022 , G06F2217/62
摘要： Asynchronous behavior of a circuit is modeled by modifying latches in a netlist to add an extra port to the latches, e.g., a single-port latch is transformed into a dual-port latch. Each input port has an enable line and a data input. The data input in the added port is a feedback line from the latch output, and the enable line in the added port is the logical NOR of all of the original enable lines. By adding this extra latch port in the higher-level model, it becomes possible to introduce assertion logic to ensure that one and only one latch port for a given latch is ever active during the same simulation cycle. The model can then be tested earlier in the design methodology prior to the availability of the post-synthesis netlist. The model can also be used in both simulation and formal or semi-formal verification.
摘要翻译：电路的异步行为是通过修改网表中的锁存器来增加锁存器的额外端口来建模的，例如，单端口锁存器被转换成双端口锁存器。每个输入端口都有一个使能线和数据输入。添加端口中输入的数据是来自锁存器输出的反馈线，加入端口中的使能线为所有原始使能线的逻辑或。通过在更高级别的模型中添加这个额外的锁存端口，可以引入断言逻辑，以确保给定锁存器中的一个和唯一一个锁存端口在同一仿真周期内始终处于活动状态。然后可以在设计方法之前对该模型进行测试，然后才能获得后合成网表。该模型也可用于模拟和正式或半正式验证。

4. 发明申请

US20070198238A1 Modeling asynchronous behavior from primary inputs and latches 失效
标题翻译：从主要输入和锁存器建模异步行为
公开(公告)号：US20070198238A1
公开(公告)日：2007-08-23
申请号：US11360906
申请日：2006-02-23
申请人： Zoltan Hidvegi , Yee Ja , Bradley Nelson
发明人： Zoltan Hidvegi , Yee Ja , Bradley Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： Asynchronous behavior of a circuit is emulated by modifying a netlist to insert additional logic at a driving element such as a latch. The additional logic outputs one of (i) a present output from the driving element, (ii) a delayed output from the driving element, or (iii) a random value, which drives downstream logic. The output of the additional logic is selectively responsive to a user-controlled skew enable input. The invention allows for simpler data skew logic transformations which are applicable to both latches and primary inputs, with no dependencies on any clock net.
摘要翻译：通过修改网表以在诸如锁存器的驱动元件处插入附加逻辑来仿真电路的异步行为。附加逻辑输出（i）来自驱动元件的当前输出，（ii）来自驱动元件的延迟输出，或（iii）驱动下游逻辑的随机值中的一个。附加逻辑的输出选择性地响应于用户控制的偏移使能输入。本发明允许更简单的数据偏移逻辑变换，其可应用于锁存器和主输入，而不依赖于任何时钟网。

5. 发明申请

US20070098020A1 Methods and arrangements to model an asynchronous interface 审中-公开
标题翻译：用于建模异步接口的方法和安排
公开(公告)号：US20070098020A1
公开(公告)日：2007-05-03
申请号：US11260557
申请日：2005-10-27
申请人： Yee Ja , Bradley Nelson
发明人： Yee Ja , Bradley Nelson
IPC分类号： H04L12/26 , H04J3/06 , H04J1/16
CPC分类号： G06F13/4291
摘要： Methods and arrangements to model an asynchronous interface are disclosed. Embodiments include transformations, code, state machines or other logic to generate a skew pattern for a semi-static or time-constrained, asynchronous interface and employ the skew pattern in data transfers during a time interval in which the asynchronous interface. Embodiments may then alter the skew pattern in at the expiration of the time interval. In many embodiments, changes to the skew pattern may be substantially non-deterministic. In other embodiments, changes to the skew pattern may follow a heuristic or other dynamic or pre-determined pattern.
摘要翻译：公开了对异步接口进行建模的方法和布置。实施例包括转换，代码，状态机或其他逻辑，以产生用于半静态或时间约束的异步接口的偏斜模式，并且在异步接口的时间间隔期间采用数据传输中的偏斜模式。然后，实施例可以在时间间隔期满时改变偏斜模式。在许多实施例中，对偏斜图案的改变可以是基本上不确定的。在其他实施例中，偏斜图案的改变可以遵循启发式或其他动态或预定图案。

6. 发明申请

US20060190883A1 System and method for unfolding/replicating logic paths to facilitate propagation delay modeling 失效
标题翻译：用于展开/复制逻辑路径以促进传播延迟建模的系统和方法
公开(公告)号：US20060190883A1
公开(公告)日：2006-08-24
申请号：US11054903
申请日：2005-02-10
申请人： Yee Ja , Bradley Nelson
发明人： Yee Ja , Bradley Nelson
IPC分类号： G06F17/50
CPC分类号： G06F17/5031
摘要： A system and method for unfolding/replicating logic paths to facilitate propagation delay modeling are provided. With the system and method, nets of an integrated circuit design are unfolded and logic of these nets is replicated such that each leg of a fanout can be driven independently from the signal source. In order to unfold the nets, the nets and logic are replicated in the netlist and connected to replicated source and endpoints. These new nets in the netlist may then be driven separately such that a different propagation delay along different nets from the same source may be simulated. In this way, a level of propagation delay may be abstracted into the modeling by driving or delaying each path separately. The transitioning value will then appear to have differing arrival times from the perspective of the sinks.
摘要翻译：提供了用于展开/复制逻辑路径以促进传播延迟建模的系统和方法。利用系统和方法，集成电路设计的网络被展开，并且复制这些网络的逻辑，使得扇出的每个支路可以独立于信号源被驱动。为了展开网络，网络和逻辑在网表中被复制，并连接到复制的源和端点。网表中的这些新网可以单独驱动，从而可以模拟来自相同源的不同网络的不同传播延迟。以这种方式，可以通过单独驱动或延迟每个路径将传播延迟的级别提取到建模中。从汇的角度来看，过渡值似乎有不同的到达时间。

7. 发明申请

US20070244685A1 METHOD FOR MODELING METASTABILITY DECAY USING FENCE LOGIC INSERTION 审中-公开
标题翻译：使用智能逻辑插入建立均匀性衰减的方法
公开(公告)号：US20070244685A1
公开(公告)日：2007-10-18
申请号：US11279911
申请日：2006-04-17
申请人： Yee Ja , Bradley Nelson , Raymond Schuppe
发明人： Yee Ja , Bradley Nelson , Raymond Schuppe
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： A method for modeling metastablilty decay in digital circuit devices includes identifying each latch at a receiving end of an asynchronous clock boundary, enumerating a latch depth for each latch within logical influence of each of the identified receive latches, and inserting fence logic immediately prior to the input of each latch at an enumerated depth, n, wherein n represents a latch depth at which an indeterminate metastable value received at the asynchronous boundary decays to a random logic value. The fence logic converts an identified indeterminate value to a random logic value, and any indeterminate value initially received is allowed to propagate up to the fence logic.
摘要翻译：一种用于建模数字电路设备中的转移衰减的方法包括识别异步时钟边界的接收端处的每个锁存器，在每个所标识的接收锁存器的逻辑影响内列举每个锁存器的锁存深度，并在紧接着每个锁存器的输入在枚举深度n处，其中n表示在异步边界处接收的不确定亚稳定值衰减到随机逻辑值的锁存深度。栅栏逻辑将识别的不确定值转换为随机逻辑值，并且允许最初接收的任何不确定值传播到栅栏逻辑。

8. 发明授权

US06993729B2 Method, system and program product for specifying a dial group for a digital system described by a hardware description language (HDL) model 失效
标题翻译：用于指定由硬件描述语言（HDL）模型描述的数字系统的拨号组的方法，系统和程序产品
公开(公告)号：US06993729B2
公开(公告)日：2006-01-31
申请号：US10425070
申请日：2003-04-28
申请人： Bradley Nelson , Wolfgang Roesner , Hugh Shen , Derek Edward Williams
发明人： Bradley Nelson , Wolfgang Roesner , Hugh Shen , Derek Edward Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022 , G06F17/5045
摘要： A statement in at least one hardware definition language (HDL) file specifies a plurality of design entities representing a functional portion of a digital system. The plurality of design entities have an associated plurality of configuration latches each having a plurality of different possible latch values, where different sets of latch values for the plurality of configuration latches correspond to different configurations of the functional portion of the digital system. With a statement in the at least one HDL file, a Dial group entity is associated with one of the plurality of design entities. The Dial group entity has a Dial list listing a plurality of Dial entities whose settings collectively control which set of latch values is loaded into the plurality of configuration latches. Membership in the Dial group constrains all instances of the plurality of Dial entities belonging to a particular instance of the Dial group to be set as a group.
摘要翻译：至少一种硬件定义语言（HDL）文件中的语句指定表示数字系统的功能部分的多个设计实体。多个设计实体具有相关联的多个配置锁存器，每个配置锁存器具有多个不同的可能的锁存值，其中用于多个配置锁存器的不同的锁存值集合对应于数字系统的功能部分的不同配置。通过至少一个HDL文件中的语句，Dial组实体与多个设计实体之一相关联。拨号组实体具有列出多个拨号实体的拨号列表，其多个拨号实体的设置共同控制哪个锁存值集合被加载到多个配置锁存器中。 Dial组中的成员资格限制属于Dial组的特定实例的多个Dial实体的所有实例被设置为一组。

9. 发明申请

US20050149309A1 Method, system and program product supporting user tracing in a simulator 失效
标题翻译：在模拟器中支持用户跟踪的方法，系统和程序产品
公开(公告)号：US20050149309A1
公开(公告)日：2005-07-07
申请号：US10750590
申请日：2003-12-31
申请人： Bradley Nelson , Wolfgang Roesner , Derek Williams
发明人： Bradley Nelson , Wolfgang Roesner , Derek Williams
IPC分类号： G06F17/50
CPC分类号： G06F17/5022
摘要： According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.
摘要翻译：根据指定用于数字设计的仿真的跟踪阵列的方法，模拟模型中的一个或多个实体用一个或多个硬件描述语言（HDL）文件中的一个或多个语句来指定。另外，在一个或多个HDL文件中的一个或多个语句中指定用于存储通过模拟仿真模型生成的数据的跟踪数组。随后可以处理HDL文件以创建包含设计实体内的至少一个设计实体和跟踪阵列的模拟模型，用于存储关于所关心的指定信号的跟踪数据。

10. 发明授权

US07536288B2 Method, system and program product supporting user tracing in a simulator 失效
标题翻译：在模拟器中支持用户跟踪的方法，系统和程序产品
公开(公告)号：US07536288B2
公开(公告)日：2009-05-19
申请号：US10750590
申请日：2003-12-31
申请人： Bradley Nelson , Wolfgang Roesner , Derek Edward Williams
发明人： Bradley Nelson , Wolfgang Roesner , Derek Edward Williams
IPC分类号： G06F17/50 , G06F9/45 , G06F9/455
CPC分类号： G06F17/5022
摘要： According to a method of specifying a trace array for simulation of a digital design, one or more entities within a simulation model are specified with one or more statements in one or more hardware description language (HDL) files. In addition, a trace array for storing data generated through simulation of the simulation model is specified in one or more statements in the one or more HDL files. The HDL files may subsequently be processed to create a simulation model containing at least one design entity and a trace array within the design entity for storing trace data regarding specified signals of interest.
摘要翻译：根据指定用于数字设计的仿真的跟踪阵列的方法，模拟模型中的一个或多个实体用一个或多个硬件描述语言（HDL）文件中的一个或多个语句来指定。另外，在一个或多个HDL文件中的一个或多个语句中指定用于存储通过模拟仿真模型生成的数据的跟踪数组。随后可以处理HDL文件以创建包含设计实体内的至少一个设计实体和跟踪阵列的模拟模型，用于存储关于所关心的指定信号的跟踪数据。

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