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1. 发明授权

US07809094B2 Method and apparatus for providing cancellation of harmonics signals with modulated signals for multi-channels 有权
标题翻译：用于提供多通道调制信号的谐波信号消除的方法和装置
公开(公告)号：US07809094B2
公开(公告)日：2010-10-05
申请号：US11872667
申请日：2007-10-15
申请人： Junyi Xu , Binfan Liu , Vladimir Radionov , Weimin Zhang
发明人： Junyi Xu , Binfan Liu , Vladimir Radionov , Weimin Zhang
IPC分类号： H03D1/04
CPC分类号： H04B1/0475
摘要： A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.
摘要翻译：用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。

2. 发明授权

US08401092B1 Multi-reference clock synchronization techniques 失效
标题翻译：多参考时钟同步技术
公开(公告)号：US08401092B1
公开(公告)日：2013-03-19
申请号：US12848073
申请日：2010-07-30
申请人： Binfan Liu , Junyi Xu , Weimin Zhang
发明人： Binfan Liu , Junyi Xu , Weimin Zhang
IPC分类号： H04B3/00
CPC分类号： H04L7/0037 , H03L7/06 , H04J3/0638 , H04J3/0658 , H04L27/36
摘要： Efficient synchronization techniques that support multiple reference clocks in an EQAM device. Consider a plurality of different modulators in the EQAM device receiving data from a corresponding plurality of different sources having corresponding different timing references (i.e., different source reference clocks). To accommodate this, the modulators all operate using a common system clock, and each modulator is provided with a phase synchronizer. The phase synchronizer synchronizes the modulated symbol phases to the corresponding reference clock.
摘要翻译：在EQAM设备中支持多个参考时钟的高效同步技术。考虑在EQAM设备中接收来自具有对应的不同定时参考（即，不同的源参考时钟）的相应多个不同源的数据的多个不同调制器。为了适应这一点，调制器都使用公共系统时钟进行操作，并且每个调制器都配备有相位同步器。相位同步器将调制的符号相位同步到相应的参考时钟。

3. 发明申请

US20090096514A1 METHOD AND APPARATUS FOR PROVIDING CANCELLATION OF HARMONICS SIGNALS WITH MODULATED SIGNALS FOR MULTI-CHANNELS 有权
标题翻译：用于多通道调制信号提取谐波信号的方法和装置
公开(公告)号：US20090096514A1
公开(公告)日：2009-04-16
申请号：US11872667
申请日：2007-10-15
申请人： Junyi Xu , Binfan Liu , Vladimir Radionov , Weimin Zhang
发明人： Junyi Xu , Binfan Liu , Vladimir Radionov , Weimin Zhang
IPC分类号： H04B1/10
CPC分类号： H04B1/0475
摘要： A device and method for canceling or attenuating harmonics noise without distorting the incoming signal. An exemplary device includes the use of an estimation loop to generate an artificial signal to eliminate or attenuate the influence of harmonics. The estimation loop includes a mixer adapted to produce a mixed signal by processing or combining the incoming signal and the artificial signal. The estimation loop includes an error detector, a low-pass filter, a parameter estimator, and a numerically controlled oscillator. The parameter estimator produces information relating to the phase, frequency, and amplitude of an incoming harmonics spur and will be used by the numerically controlled oscillator to generate the artificial signal. If the mixed signal contains relatively low levels of harmonics residuals, the mixed signal is produced at the output in lieu of the incoming signal.
摘要翻译：用于消除或衰减谐波噪声而不使输入信号失真的装置和方法。示例性装置包括使用估计环路来产生人造信号以消除或衰减谐波的影响。估计环路包括适于通过处理或组合输入信号和人造信号来产生混合信号的混频器。估计回路包括误差检测器，低通滤波器，参数估计器和数控振荡器。参数估计器产生与输入谐波支路的相位，频率和幅度相关的信息，并由数控振荡器用于产生人为信号。如果混合信号包含较低水平的谐波残差，则在输出端产生混合信号来代替输入信号。

4. 发明申请

US20110113305A1 HIGH THROUGHPUT INTERLEAVER / DEINTERLEAVER 失效
标题翻译：高通量交换机/去除器
公开(公告)号：US20110113305A1
公开(公告)日：2011-05-12
申请号：US12652167
申请日：2010-01-05
申请人： Binfan Liu , Junyi Xu
发明人： Binfan Liu , Junyi Xu
IPC分类号： H03M13/05 , G06F12/02 , G06F12/06 , G06F11/10
CPC分类号： G11C7/1072 , H03M13/2707 , H03M13/2721 , H03M13/2732 , H03M13/2906 , H03M13/2936
摘要： Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.
摘要翻译：提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。每个块包括两个数据序列。每个数据序列还包括要交织/解交织的预定数量的数据字。当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

5. 发明申请

US20060136768A1 Method and system for multi-program clock recovery and timestamp correction 失效
标题翻译：多程序时钟恢复和时间戳校正的方法和系统
公开(公告)号：US20060136768A1
公开(公告)日：2006-06-22
申请号：US10996582
申请日：2004-11-23
申请人： Binfan Liu , Thomas Ayers , Weimin Zhang
发明人： Binfan Liu , Thomas Ayers , Weimin Zhang
IPC分类号： G06F1/12
CPC分类号： H04N21/4305 , H04N5/4401 , H04N21/4307
摘要： A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.
摘要翻译：解码器包括被配置为接收节目并提取嵌入在节目中的定时信息和时间戳的传输引擎。加法器被配置为将一组定时偏移量添加到定时信息组，以便从第一时间基准到第二时间基准来调整定时信息。定时偏移和定时信息的和被称为映射定时信息。校正引擎被配置为在程序中遇到定时信息时更新定时偏移，并且偏移寄存器被配置为：接收定时偏移，存储定时偏移，并将定时偏移传送给加法器。加法器还被配置为将时间偏移量添加到时间戳，以便调整从第一时间到第二时间的时间戳的时间基准。程序是被配置为接收调整的时间戳以解码程序的解码器。

6. 发明授权

US08352834B2 High throughput interleaver / deinterleaver 失效
标题翻译：高吞吐量交织器/解交织器
公开(公告)号：US08352834B2
公开(公告)日：2013-01-08
申请号：US12652167
申请日：2010-01-05
申请人： Binfan Liu , Junyi Xu
发明人： Binfan Liu , Junyi Xu
IPC分类号： G06F11/00 , H03M13/00 , H04L1/18 , G11C29/00
CPC分类号： G11C7/1072 , H03M13/2707 , H03M13/2721 , H03M13/2732 , H03M13/2906 , H03M13/2936
摘要： Systems and methods for performing high-speed multi-channel forward error correction using external DDR SDRAM is provided. According to one exemplary aspect, an interleaver/deinterleaver performs both read and write accesses to the DDR SDRAM that are burst-oriented by hiding active and precharge cycles in order to achieve high data rate operations. The interleaver/deinterleaver accesses data in the DDR SDRAM as read blocks and write blocks. Each block includes two data sequences. Each data sequence further includes a predetermined number of data words to be interleaved/deinterleaved. The PRECHARGE and ACTIVE command for one data sequence is issued when a preceding data sequence is being processed. Data in one read/write data sequence has the same row address within the same bank of the DDR SDRAM.
摘要翻译：提供了使用外部DDR SDRAM执行高速多通道前向纠错的系统和方法。根据一个示例性方面，交织器/解交织器通过隐藏有效和预充电周期来对通过突发定向的DDR SDRAM执行读和写访问，以实现高数据速率操作。交织器/解交织器将DDR SDRAM中的数据作为读取块和写入块访问。每个块包括两个数据序列。每个数据序列还包括要交织/解交织的预定数量的数据字。当处理前面的数据序列时，会发出一个数据序列的PRECHARGE和ACTIVE命令。一个读/写数据序列中的数据在DDR SDRAM的同一组内具有相同的行地址。

7. 发明授权

US07710965B2 Method and system for multi-program clock recovery and timestamp correction 失效
标题翻译：多程序时钟恢复和时间戳校正的方法和系统
公开(公告)号：US07710965B2
公开(公告)日：2010-05-04
申请号：US10996582
申请日：2004-11-23
申请人： Binfan Liu , Thomas Ayers , Weimin Zhang
发明人： Binfan Liu , Thomas Ayers , Weimin Zhang
IPC分类号： H04J3/06
CPC分类号： H04N21/4305 , H04N5/4401 , H04N21/4307
摘要： A decoder includes a transport engine configured to receive programs and extract timing information and timestamps embedded in the programs. An adder is configured to add a set of timing offsets to the sets of timing information to adjust the timing information from a first time basis to a second time basis. Sums of the timing offsets and the timing information are referred to the mapped-timing information. A correction engine is configured to update the timing offsets as timing information is encountered in the programs, and an offset register is configured to: receive the timing offsets, store the timing offsets, and transfer the timing offsets to the adder. The adder is also configured to add the timing offsets to the timestamps to adjust the time basis of the timestamps from the first time basis to the second time basis. A program is decoder configured to receive the adjusted timestamps to decode the programs.
摘要翻译：解码器包括被配置为接收节目并提取嵌入在节目中的定时信息和时间戳的传输引擎。加法器被配置为将一组定时偏移量添加到定时信息组，以便从第一时间基准到第二时间基准来调整定时信息。定时偏移和定时信息的和被称为映射定时信息。校正引擎被配置为在程序中遇到定时信息时更新定时偏移，并且偏移寄存器被配置为：接收定时偏移，存储定时偏移，并将定时偏移传送给加法器。加法器还被配置为将时间偏移量添加到时间戳，以便调整从第一时间到第二时间的时间戳的时间基准。程序是被配置为接收调整的时间戳以解码程序的解码器。

8. 发明授权

US07065696B1 Method and system for providing high-speed forward error correction for multi-stream data 失效
标题翻译：为多流数据提供高速前向纠错的方法和系统
公开(公告)号：US07065696B1
公开(公告)日：2006-06-20
申请号：US10412745
申请日：2003-04-11
申请人： Binfan Liu , Zhongqian Wang , Weimin Zhang
发明人： Binfan Liu , Zhongqian Wang , Weimin Zhang
IPC分类号： H03M13/29
CPC分类号： H03M13/256 , H03M13/2732 , H03M13/2936 , H03M13/333 , H04L1/0052 , H04L1/0054 , H04L1/006 , H04L1/0065
摘要： A system for providing a high-speed implementation for multi-stream forward error correction (FEC) is provided. According to one exemplary aspect, the system is able to provide block-based multi-stream FEC that reduces the power consumption when compared with conventional symbol-based FEC. The system provides a pipeline architecture for multi-stream FEC so that modules in the system are able to respectively process blocks of data from different channels or data streams.
摘要翻译：提供了一种用于提供用于多流前向纠错（FEC）的高速实现的系统。根据一个示例性方面，与传统的基于符号的FEC相比，该系统能够提供降低功耗的基于块的多流FEC。该系统为多流FEC提供流水线架构，使得系统中的模块能够分别处理来自不同信道或数据流的数据块。

9. 发明授权

US07720147B2 Method and system for providing a high speed multi-stream MPEG processor 有权
标题翻译：提供高速多流MPEG处理器的方法和系统
公开(公告)号：US07720147B2
公开(公告)日：2010-05-18
申请号：US10888551
申请日：2004-07-09
申请人： Weimin Zhang , Binfan Liu , Zhongqiang Wang
发明人： Weimin Zhang , Binfan Liu , Zhongqiang Wang
IPC分类号： H04N7/12
CPC分类号： H04N21/2362 , H04N19/174 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N21/40
摘要： An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.
摘要翻译：提供MPEG处理器。根据处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。然后从芯片外存储器中检索通道的相应数据进行处理。然后对所检索的数据进行解码。解码结果和相关信息存储在片外存储器中。可用于解码后续数据的部分或全部相关信息存储在片上存储器中。当需要显示视频图像时，然后从片外存储器检索所需的相应数据，并将其提供给与模拟显示装置兼容的格式的模拟编码器进行编码。

10. 发明申请

US20050031042A1 Method and system for providing a high speed multi-stream MPEG processor 有权
标题翻译：提供高速多流MPEG处理器的方法和系统
公开(公告)号：US20050031042A1
公开(公告)日：2005-02-10
申请号：US10888551
申请日：2004-07-09
申请人： Weimin Zhang , Binfan Liu , Zhongqiang Wang
发明人： Weimin Zhang , Binfan Liu , Zhongqiang Wang
IPC分类号： G06K9/36 , H01L20060101 , H04N5/00 , H04N5/272 , H04N7/12 , H04N7/26 , H04N7/50
CPC分类号： H04N21/2362 , H04N19/174 , H04N19/423 , H04N19/436 , H04N19/44 , H04N19/61 , H04N21/40
摘要： An MPEG processor is provided. According to one aspect of the processor, multiple MPEG data streams for corresponding channels are individually stored in an off-chip memory. Corresponding data for a channel is then retrieved from the off-chip memory for processing. The retrieved data is then decoded. The decoded results and associated information are stored on the off-chip memory. Some or all of the associated information that can be used for decoding subsequent data is stored in an on-chip memory. When video images need to be displayed, the corresponding data that is needed for that purpose is then retrieved from the off-chip memory and provided to an analog encoder for encoding in a format that is compatible with an analog display device.
摘要翻译：提供MPEG处理器。根据处理器的一个方面，用于相应通道的多个MPEG数据流被单独存储在片外存储器中。然后从芯片外存储器中检索通道的相应数据进行处理。然后对所检索的数据进行解码。解码结果和相关信息存储在片外存储器中。可用于解码后续数据的部分或全部相关信息存储在片上存储器中。当需要显示视频图像时，然后从片外存储器检索所需的相应数据，并将其提供给与模拟显示装置兼容的格式的模拟编码器进行编码。

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