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    • 2. 发明授权
    • High speed dynamic comparative latch
    • 高速动态比较锁
    • US08339158B2
    • 2012-12-25
    • US12981514
    • 2010-12-30
    • Bin LiGuosheng Wu
    • Bin LiGuosheng Wu
    • G01R19/00H03F3/45
    • H03K3/356173H03K5/249
    • A dynamic high-speed comparative latch comprises a pre-amplifier unit for enlarging input differential signals, a regenerating latch unit for latching outputted differential signals from the pre-amplifier unit by using a positive feedback, specifically, converting the output of the pre-amplifier unit into a latched result at a first state of a clock cycle, and then retaining the latched result and simultaneously resetting relevant nodes at a second state opposite to the first state of the clock cycle, and a latch unit for outputting the effective outputted value of the regenerating latch unit when the regenerating latch unit being in a retaining state. The pre-amplifier unit is connected with the regenerating latch unit, and the regenerating latch unit is connected with the latch unit. The pre-amplifier unit comprises only one input clock signal. The present invention has a simple structure, and ensures the correctness of the output result of the latch.
    • 动态高速比较锁存器包括用于放大输入差分信号的前置放大器单元,用于通过使用正反馈来锁存来自前置放大器单元的输出差分信号的再生锁存单元,具体地说,转换前置放大器的输出 在时钟周期的第一状态下将其锁存到锁存结果中,然后保持锁存结果并且在与时钟周期的第一状态相反的第二状态下同时复位相关节点;以及锁存单元,用于输出有效输出值 当再生闩锁单元处于保持状态时,再生闩锁单元。 前置放大器单元与再生锁存单元连接,再生锁存单元与闩锁单元连接。 前置放大器单元仅包括一个输入时钟信号。 本发明具有简单的结构,并且确保了闩锁的输出结果的正确性。
    • 3. 发明申请
    • High-speed data compared latch with auto-adjustment of offset
    • 高速数据比较锁存器与自动调整偏移量
    • US20100315149A1
    • 2010-12-16
    • US12797608
    • 2010-06-10
    • Guosheng WuBin Li
    • Guosheng WuBin Li
    • H03L5/00
    • H03K3/356139
    • A high-speed data compared latch with auto-adjustment of offset, includes input pair transistors P, input pair transistors N, a compared latch module, an input control module, an output control module and a offset logic control module, the offset logic control module creates two control signals that regulate the number of input pair transistors P and input pair transistors N respectively according to reset signal RESET and the latched output of the compared latch module, and achieve self correcting of offset through regulating the number of the input pair transistors P and the input pair transistors N. The present invention is a feedback mechanism, automatically trimming the number of differential input pair to achieve the trimming differential pair operating point and the threshold voltage, eliminate the process variation, and latch on more precise control match the differential input pair transistors of the high-speed data compared latch in receiver accurately.
    • 具有自动调整偏移量的高速数据比较锁存器,包括输入对晶体管P,输入对晶体管N,比较锁存模块,输入控制模块,输出控制模块和偏移逻辑控制模块,偏移逻辑控制 模块根据复位信号RESET和被锁存的比较锁存模块的输出产生分别调节输入对晶体管P和输入对晶体管N的数量的两个控制信号,并通过调节输入对晶体管的数量来实现偏移的自校正 P和输入对晶体管N.本发明是一种反馈机制,自动修整差分输入对的数量,以实现微调差分对工作点和阈值电压,消除过程变化,并锁定更精确的控制匹配 差分输入对晶体管的高速数据比较锁存在接收机中的准确。