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1. 发明授权

US06594024B1 Monitor CMP process using scatterometry 有权
标题翻译：使用散点法监测CMP过程
公开(公告)号：US06594024B1
公开(公告)日：2003-07-15
申请号：US09886863
申请日：2001-06-21
申请人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Carmen Morales
发明人： Bhanwar Singh , Ramkumar Subramanian , Khoi A. Phan , Bharath Rangarajan , Carmen Morales
IPC分类号： G01B1128
CPC分类号： B24B37/005 , B24B49/12 , G01N21/47 , G01N21/9501 , H01L21/30625
摘要： One aspect of the present invention relates to an in-line system for monitoring and optimizing an on-going CMP process in order to determine a CMP process endpoint comprising a wafer, wherein the wafer is subjected to the CMP process; a CMP process monitoring system for generating a signature related to wafer dimensions for the wafer subjected to the CMP process; and a signature library to which the generated signature is compared to determine a state of the wafer. Another aspect relates to an in-line method for monitoring and optimizing an on-going CMP process involving providing a wafer, wherein the wafer is subjected to a CMP process; generating a signature associated with the wafer; comparing the generated signature to a signature library to determine a state of the wafer; and using a closed-loop feedback control system for modifying the on-going CMP process according to the determined state of the wafer.
摘要翻译：本发明的一个方面涉及用于监测和优化正在进行的CMP工艺的在线系统，以便确定包括晶片的CMP工艺端点，其中晶片经历CMP工艺; 用于生成与经历CMP处理的晶片的晶片尺寸相关的签名的CMP过程监控系统; 以及生成的签名被比较的签名库，以确定晶片的状态。另一方面涉及用于监测和优化涉及提供晶片的正在进行的CMP工艺的在线方法，其中所述晶片经受CMP工艺; 产生与晶片相关联的签名; 将生成的签名与签名库进行比较以确定晶片的状态; 以及使用闭环反馈控制系统来根据所确定的晶片状态来修正正在进行的CMP工艺。

2. 发明授权

US06459945B1 System and method for facilitating determining suitable material layer thickness in a semiconductor device fabrication process 失效
标题翻译：用于在半导体器件制造工艺中有助于确定合适的材料层厚度的系统和方法
公开(公告)号：US06459945B1
公开(公告)日：2002-10-01
申请号：US09311223
申请日：1999-05-13
申请人： Bhanwar Singh , Carmen Morales , Bharath Rangarajan
发明人： Bhanwar Singh , Carmen Morales , Bharath Rangarajan
IPC分类号： G06F1900
CPC分类号： B24B37/013 , B24B49/04 , H01L21/67253 , H01L22/34
摘要： The present invention relates to a test wafer for use in optimizing a process. The test wafer includes a substrate and a material layer formed over the substrate, wherein the material layer includes N number of test regions (N being an integer greater than one). At least one of the test regions has a material layer thickness different from another of the test regions. A spindle drive system is also provided for driving at least one spindle. One end of the at least one spindle is coupled to a polishing pad, which is employed in forming the test regions.
摘要翻译：本发明涉及用于优化工艺的测试晶片。测试晶片包括衬底和形成在衬底上的材料层，其中材料层包括N个测试区域（N是大于1的整数）。测试区域中的至少一个具有与另一个测试区域不同的材料层厚度。还提供用于驱动至少一个主轴的主轴驱动系统。所述至少一个心轴的一端连接到用于形成所述测试区域的抛光垫。

3. 发明授权

US07080330B1 Concurrent measurement of critical dimension and overlay in semiconductor manufacturing 有权
标题翻译：半导体制造中临界尺寸和覆盖层并行测量
公开(公告)号：US07080330B1
公开(公告)日：2006-07-18
申请号：US10379738
申请日：2003-03-05
申请人： Bryan Choo , Bharath Rangarajan , Bhanwar Singh , Carmen Morales
发明人： Bryan Choo , Bharath Rangarajan , Bhanwar Singh , Carmen Morales
IPC分类号： G06F17/50
CPC分类号： G03F7/70633 , G01N21/4788 , G01N21/956 , G03F7/70625
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. One or more structures formed on a wafer matriculating through the process facilitate concurrent measurement of critical dimensions and overlay via scatterometry or a scanning electron microscope (SEM). The concurrent measurements mitigate fabrication inefficiencies, thereby reducing time and real estate required for the fabrication process. The measurements can be utilized to generate feedback and/or feed-forward data to selectively control one or more fabrication components and/or operating parameters associated therewith to achieve desired critical dimensions and to mitigate overlay error.
摘要翻译：公开了用于监测和控制半导体制造工艺的系统和方法。通过该过程形成的晶片上形成的一个或多个结构便于同时测量临界尺寸并通过散射测量法或扫描电子显微镜（SEM）覆盖。同时测量可减轻制造效率低下，从而减少制造过程所需的时间和空间。可以利用这些测量来产生反馈和/或前馈数据，以选择性地控制一个或多个制造部件和/或与之相关联的操作参数以实现所需的临界尺寸并减轻重叠误差。

4. 发明授权

US07158896B1 Real time immersion medium control using scatterometry 失效
标题翻译：实时浸入介质控制采用散射法
公开(公告)号：US07158896B1
公开(公告)日：2007-01-02
申请号：US10978604
申请日：2004-11-01
申请人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
发明人： Bhanwar Singh , Srikanteswara Dakshina-Murthy , Khoi A. Phan , Ramkumar Subramanian , Bharath Rangarajan , Iraj Emami
IPC分类号： G06F19/00
CPC分类号： G03F7/70916 , G03F7/2041 , G03F7/70341
摘要： Systems and/or methods are disclosed for measuring and/or controlling an amount of impurity that is dissolved within an immersion medium employed with immersion lithography. The impurity can be photoresist from a photoresist layer coated upon a substrate surface. A known grating structure is built upon the substrate. A real time immersion medium monitoring component facilitates measuring and/or controlling the amount of impurities dissolved within the immersion medium by utilizing light scattered from the known grating structure.
摘要翻译：公开了用于测量和/或控制溶解在浸入式光刻中使用的浸渍介质中的杂质量的系统和/或方法。杂质可以是来自涂覆在基材表面上的光致抗蚀剂层的光致抗蚀剂。已知的光栅结构被构建在衬底上。实时浸没介质监测部件通过利用从已知光栅结构散射的光来便于测量和/或控制溶解在浸没介质中的杂质的量。

5. 发明授权

US07078348B1 Dual layer patterning scheme to make dual damascene 失效
标题翻译：双层图案方案制作双镶嵌
公开(公告)号：US07078348B1
公开(公告)日：2006-07-18
申请号：US09893188
申请日：2001-06-27
申请人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
发明人： Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan , Michael K. Templeton
IPC分类号： H01L21/302 , H01L21/3065
CPC分类号： H01L21/31144 , H01L21/76807 , H01L21/76811 , H01L21/76813
摘要： One aspect of the present invention relates to a method for making a dual damascene pattern in an insulative layer in a single etch process involving providing a wafer having at least one insulative layer formed thereon; depositing a first photoresist layer over the at least one insulative layer; patterning a first image into the first photoresist layer; curing the first patterned photoresist layer; depositing a second photoresist layer over the first patterned photoresist layer; patterning a second image into the second photoresist layer; and etching the at least one insulative layer through the first patterned photoresist layer and the second patterned photoresist layer simultaneously in the single etch process.
摘要翻译：本发明的一个方面涉及在单一蚀刻工艺中在绝缘层中制造双镶嵌图案的方法，该方法包括提供其上形成有至少一个绝缘层的晶片; 在所述至少一个绝缘层上沉积第一光致抗蚀剂层; 将第一图像图案化成第一光致抗蚀剂层; 固化第一图案化光致抗蚀剂层; 在所述第一图案化光致抗蚀剂层上沉积第二光致抗蚀剂层; 将第二图像图案化成第二光致抗蚀剂层; 以及在单次蚀刻工艺中同时蚀刻通过第一图案化光致抗蚀剂层和第二图案化光致抗蚀剂层的至少一个绝缘层。

6. 发明授权

US07052575B1 System and method for active control of etch process 有权
标题翻译：用于主动控制蚀刻工艺的系统和方法
公开(公告)号：US07052575B1
公开(公告)日：2006-05-30
申请号：US09845454
申请日：2001-04-30
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： C23F1/00
CPC分类号： H01L21/67253 , H01J37/32935 , H01L21/67063 , H01L22/34
摘要： A system for regulating an etch process is provided. The system includes one or more light sources, each light source directing light to one or more features and/or gratings on a wafer. Light reflected from the features and/or gratings is collected by a measuring system, which processes the collected light. The collected light is indicative of the dimensions achieved at respective portions of the wafer. The measuring system provides etching related data to a processor that determines the acceptability of the etching of the respective portions of the wafer. The system also includes one or more etching devices, each such device corresponding to a portion of the wafer and providing for the etching thereof. The processor selectively controls the etching devices to regulate etching of the portions of the wafer.
摘要翻译：提供了一种用于调节蚀刻工艺的系统。该系统包括一个或多个光源，每个光源将光引导到晶片上的一个或多个特征和/或光栅。从特征和/或光栅反射的光由测量系统收集，该系统处理收集的光。所收集的光指示在晶片的相应部分处获得的尺寸。测量系统向处理器提供蚀刻相关数据，该处理器确定晶片的相应部分的蚀刻的可接受性。该系统还包括一个或多个蚀刻装置，每个这样的装置对应于晶片的一部分并提供其蚀刻。处理器选择性地控制蚀刻装置来调节晶片的部分的蚀刻。

7. 发明授权

US07001830B2 System and method of pattern recognition and metrology structure for an X-initiative layout design 失效
标题翻译：用于X主动布局设计的模式识别和计量结构的系统和方法
公开(公告)号：US07001830B2
公开(公告)日：2006-02-21
申请号：US10653309
申请日：2003-09-02
申请人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
发明人： Khoi A. Phan , Bharath Rangarajan , Bhanwar Singh
IPC分类号： H01L21/20 , H01L21/36
CPC分类号： G03F7/70625 , G03F7/70633 , G03F9/7076 , Y10S438/975
摘要： The present invention relates to inspection methods and systems utilized to provide a best means for inspection of a wafer. The methods and systems include wafer-to-reticle alignment, layer-to-layer alignment and wafer surface feature inspection. The wafer-to-reticle alignment is improved by the addition of diagonal lines to existing alignment marks to decrease the intersection size and corresponding area that a desired point can reside. Layer-to-layer alignment is improved in a similar manner by the addition of oblique and/or non-linear line segments to existing overlay targets. Also, providing for wafer surface inspection in a multitude of desired diagonal axes allows for more accurate feature measurement.
摘要翻译：本发明涉及用于提供用于检查晶片的最佳方法的检查方法和系统。该方法和系统包括晶片到标线片对准，层间对准和晶片表面特征检查。通过将对角线添加到现有的对准标记来减小交叉点大小和期望点可以驻留的对应区域来改善晶片到标线阵列对准。通过向现有覆盖目标添加倾斜和/或非线性线段，以类似的方式改善了层间对齐。此外，在多个所需的对角轴中提供晶片表面检查允许更精确的特征测量。

8. 发明授权

US06931618B1 Feed forward process control using scatterometry for reticle fabrication 有权
标题翻译：使用分光镜制作的散射法进行前馈过程控制
公开(公告)号：US06931618B1
公开(公告)日：2005-08-16
申请号：US10050472
申请日：2002-01-16
申请人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Cyrus E. Tabery , Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： G01B9/00 , G03F1/00 , G06F17/50 , G03H9/00
CPC分类号： G03F1/84 , G03F1/00
摘要： A system for selectively generating and feeding forward reticle fabrication data is provided. The system includes components for fabricating a reticle and a control system operatively connected to the fabricating components, where the control system can control the operation of the fabricating components. The control system bases its control of the fabricating components, at least in part, on feed forward control information generated by a processor that analyzes scatterometry based reticle fabrication data gathered from measurement components. The scatterometry data is compared to data stored in a signature data store that facilitates analyzing gathered scatterometry signatures to produce feed forward control information that can be employed to manipulate subsequent reticle fabrication processes and/or apparatus.
摘要翻译：提供了一种用于选择性地生成和馈送标线制造数据的系统。该系统包括用于制造掩模版的部件和可操作地连接到制造部件的控制系统，其中控制系统可以控制制造部件的操作。控制系统至少部分地基于由分析从测量部件收集的基于散射仪的掩模版制造数据的处理器生成的前馈控制信息的制造部件的控制。将散射测量数据与存储在签名数据存储器中的数据进行比较，其有助于分析所收集的散射光标签以产生可用于操纵随后的标线制造工艺和/或设备的前馈控制信息。

9. 发明授权

US06912438B2 Using scatterometry to obtain measurements of in circuit structures 失效
标题翻译：使用散射法获得电路结构的测量
公开(公告)号：US06912438B2
公开(公告)日：2005-06-28
申请号：US10277016
申请日：2002-10-21
申请人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
发明人： Bryan K. Choo , Bhanwar Singh , Ramkumar Subramanian , Bharath Rangarajan
IPC分类号： G01N21/47 , H01L21/66 , G06F19/00
CPC分类号： H01L22/20 , G01N21/4738 , H01L2924/0002 , H01L2924/00
摘要： A system and methodology are disclosed for monitoring and controlling a semiconductor fabrication process. Measurements are taken in accordance with scatterometry based techniques of repeating in circuit structures that evolve on a wafer as the wafer undergoes the fabrication process. The measurements can be employed to generate feed forward and/or feedback control data that can utilized to selectively adjust one or more fabrication components and/or operating parameters associated therewith to adapt the fabrication process. Additionally, the measurements can be employed in determining whether to discard the wafer or portions thereof based on a cost benefit analysis, for example. Directly measuring in circuit structures mitigates sacrificing valuable chip real estate as test grating structures may not need to be formed within the wafer, and also facilitates control over the elements that actually affect resulting chip performance.
摘要翻译：公开了用于监测和控制半导体制造工艺的系统和方法。根据基于散射法的技术进行测量，该技术在晶片经历制造过程时在晶片上发生的电路结构中重复。可以采用测量来产生可以用于选择性地调整一个或多个制造部件和/或与其相关联的操作参数以适应制造过程的前馈和/或反馈控制数据。另外，例如，可以基于成本效益分析来确定是否丢弃晶片或其部分的测量。在电路结构中的直接测量减轻了牺牲有价值的芯片的不动产，因为测试光栅结构可能不需要在晶片内形成，并且还有助于对实际影响芯片性能的元件的控制。

10. 发明授权

US06878560B1 Fab correlation system 有权
标题翻译： Fab相关系统
公开(公告)号：US06878560B1
公开(公告)日：2005-04-12
申请号：US10302091
申请日：2002-11-22
申请人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
发明人： Bharath Rangarajan , Bhanwar Singh , Ramkumar Subramanian
IPC分类号： H01L21/66
CPC分类号： H01L22/20 , G05B2219/31457 , G05B2219/32191 , G05B2219/45031 , H01L2924/0002 , H01L2924/00
摘要： A system comprised of a plurality of fabs that are operatively coupled and share data from a common framework for correlating production. The fabs can be coupled via Internet, cellular, optical, landline, microwave and satellite communication means and the like. Data can be transferred to and/or received from a central, integrated correlating entity or from several distributed correlating entities. The fabs send and receive correlating data that relates to production information such as tolerances, critical dimensions, geometry and the like. The correlating entity(s) has the capability to increase production by performing probabilistic computations on the received correlating data and utilizing the resulting information to maintain correlating parameters at remote locations. The computations performed can include such calculations as Bayesian inferencing and the like. The system inherently precludes the necessity for physically transporting parametric test entities between different fab or tooling locations.
摘要翻译：由多个工厂组成的系统，其可操作地耦合并且共享来自公共框架的数据以用于生产。该晶圆厂可以通过互联网，蜂窝，光学，固定电话，微波和卫星通信装置等耦合。可以将数据传送到中央集成的相关实体或从多个分散的相关实体传送到和/或从中央集成的相关实体接收数据。制造厂发送和接收与生产信息相关的相关数据，例如公差，关键尺寸，几何形状等。相关实体具有通过对接收到的相关数据执行概率计算并利用所得到的信息来维持远程位置处的相关参数来增加产量的能力。执行的计算可以包括诸如贝叶斯推理等的计算。该系统固有地排除了在不同晶圆厂或模具位置之间物理传输参数测试实体的必要性。

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