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    • 1. 发明授权
    • Method and apparatus for publishing part datasheets
    • 用于发布零件数据表的方法和装置
    • US06484182B1
    • 2002-11-19
    • US09330805
    • 1999-06-11
    • Betsy D. DunphyLouis EvartGeorge LundJosh MacDonaldJim L. Rogers
    • Betsy D. DunphyLouis EvartGeorge LundJosh MacDonaldJim L. Rogers
    • G06F1730
    • G06Q10/06G06F17/30958G06Q30/0201G06Q30/0633G06Q99/00Y10S707/99932Y10S707/99933Y10S707/99942Y10S707/99943Y10S707/99952
    • A method and apparatus are provided for publishing part datasheets. A part characterization database is created, and the technical characteristics of parts in the database are ascertained. In addition to parts, part groups are created based on common technical characteristics of parts, and a database tree is created based on the technical characteristics of parts and part groups. A publishing interface coupled to the part characterization database is provided for coupling a publishing tool to the part characterization database so as to provide context to the technical characteristics of one or more parts characterized within the part characterization database. A computer program product also is provided for publishing part datasheets. The computer program product comprises means for creating the part characterization database, means for ascertaining the technical characteristics of parts in the database and means for creating part groups based on common technical characteristics of parts. The computer readable medium also comprises means for creating a database tree based on the technical characteristics of parts and part groups and means for providing a publishing interface for coupling a publishing tool to the part characterization database so as to provide context to the technical characteristics of one or more parts characterized within the part characterization database.
    • 提供了一种用于发布零件数据表的方法和装置。 创建零件表征数据库,并确定数据库中零件的技术特性。 除零件之外,还可以根据部件的常见技术特点创建零件组,并根据零件和零件组的技术特点创建数据库树。 提供耦合到零件表征数据库的出版界面,用于将出版工具耦合到零件表征数据库,以便为部件特征数据库中表征的一个或多个部件的技术特性提供上下文。 还提供了用于发布部件数据表的计算机程序产品。 计算机程序产品包括用于创建零件表征数据库的装置,用于确定数据库中部件的技术特征的装置以及基于部件的共同技术特征来创建零件组的装置。 计算机可读介质还包括用于基于部件和部件组的技术特征创建数据库树的装置以及用于提供用于将发布工具耦合到部件表征数据库的发布界面的装置,以便为一个 或更多部分在部件特征数据库中表征。
    • 2. 发明授权
    • Data and data strobe circuits and operating protocol for double data rate memories
    • 数据和数据选通电路和双数据速率存储器的操作协议
    • US06529993B1
    • 2003-03-04
    • US09689090
    • 2000-10-12
    • Jim L. RogersTimothy E. Fiscus
    • Jim L. RogersTimothy E. Fiscus
    • G06F1200
    • G11C7/106G11C7/1051G11C7/1066G11C7/1078G11C7/1087G11C7/1093G11C2207/107
    • This is a circuit and protocol for relaxing the strobe to data relationship to permit the writing into and reading out of a double data rate DRAM array at data transfer rates higher than any known circuits that utilize a strobe and data protocol. This result is accomplished by modifying the prior art write circuitry by adding a strobe generator coupled to both the data input and the strobe input to control the write circuit multi-latch and by modifying the prior art read circuit by coupling the initial and enable circuit to the data drivers and adding a data compare circuit that is coupled between the memory storage array and the strobe toggle to control the strobe. In this way the present invention relaxes the use of the strobe to data relationships for reads and writes except when there are no data transitions and ends the necessity of aligning the strobe with the data eye. By so eliminating the need for strobe to data eye alignment the present invention can use smaller data eyes and data transfer rates higher than those that can be utilized by the prior art circuits.
    • 这是用于放大选通数据关系的电路和协议,以允许以高于使用选通和数据协议的任何已知电路的数据传输速率写入和读出双数据速率DRAM阵列。 这个结果是通过增加耦合到数据输入和选通输入端的选通发生器来调整现有技术的写入电路来实现的,以控制写入电路多锁存器,并且通过将初始和使能电路耦合到 数据驱动器,并添加一个数据比较电路,该电路耦合在存储器阵列与选通闪光灯之间,以控制闪光灯。 以这种方式,除了当没有数据转换并且结束将频闪与数据眼对准的必要性之外,本发明放松了使用选通对读取和写入的数据关系的用途。 通过这样消除对频闪数据眼对准的需要,本发明可以使用比现有技术电路可以利用的更小的数据眼和数据传送速率。
    • 3. 发明授权
    • Cached synchronous DRAM architecture having a mode register programmable cache policy
    • 具有模式寄存器可编程高速缓存策略的缓存同步DRAM架构
    • US06289413B1
    • 2001-09-11
    • US09360373
    • 1999-10-15
    • Jim L. RogersSteven W. TomashotDavid W. BondurantOscar Frederick Jones, Jr.Kenneth J. Mobley
    • Jim L. RogersSteven W. TomashotDavid W. BondurantOscar Frederick Jones, Jr.Kenneth J. Mobley
    • G06F1206
    • G06F12/0893G06F12/0804
    • A cached synchronous dynamic random access memory (cached SDRAM) device having a multi-bank architecture and a programmable caching policy includes a synchronous dynamic random access memory (SDRAM) bank, a synchronous static randomly addressable row register, a select logic gating circuit, and mode register for programming of the cached SDRAM to operate in a Write Transfer mode corresponding to a Normal Operation mode of a standard SDRAM during a Write cycle, and to operate in a No Write Transfer mode according to an alternate operation mode during a Write cycle, thereby operating under a first and a second caching policy, respectively. The SDRAM includes a row decoder for selecting a row of data in a memory bank array, sense amplifiers for latching the row of data selected by the row decoder, and a synchronous column selector for selecting a desired column of the row of data. The row register stores a row of data latched by the sense amplifiers and the select logic gating circuit, disposed between the sense amplifiers and the row register, selectively gates the row of data present on the bit lines to the row register in accordance to particular synchronous memory operations being performed.
    • 具有多存储体架构和可编程高速缓存策略的高速缓存的同步动态随机存取存储器(高速缓存的SDRAM)装置包括同步动态随机存取存储器(SDRAM)存储体,同步静态可随机寻址行寄存器,选择逻辑选通电路和 模式寄存器,用于在写周期期间以与标准SDRAM的正常操作模式相对应的写传输模式来操作缓存的SDRAM,并且在写周期期间根据备用操作模式在无写传输模式下操作, 从而分别在第一和第二缓存策略下运行。 SDRAM包括用于选择存储体阵列中的一行数据的行解码器,用于锁存由行解码器选择的数据行的读出放大器,以及用于选择该行数据的期望列的同步列选择器。 行寄存器存储由读出放大器锁存的一行数据,并且设置在读出放大器和行寄存器之间的选择逻辑选通电路根据特定的同步,有选择地将存在于位线上的数据行写入行寄存器 执行内存操作。