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    • 1. 发明授权
    • 2-stage large bandwidth amplifier using diodes in the parallel feedback structure
    • 2级大带宽放大器采用二极管并联反馈结构
    • US06861908B2
    • 2005-03-01
    • US10604478
    • 2003-07-24
    • Bertrand GabillardMichel RivierFabrice VoisinPhilippe Girard
    • Bertrand GabillardMichel RivierFabrice VoisinPhilippe Girard
    • H03F3/343H03F3/68
    • H03F3/3432
    • There is disclosed an improved 2-stage large bandwidth amplifier (20) comprised of two stages formed by first and second bipolar transistors (Q1,Q2) configured in common emitter that are connected in series with their emitters connected to a first supply voltage (Gnd). The input signal (Vin) is applied to the base of said first transistor via an input terminal (11), while the output signal (Vout) is available at an output terminal (12) connected to the collector of said second transistor. A parallel feedback structure (13′) is provided. It consists, in a first branch, of two diodes (D1,D2) in series connected between a second supply voltage (Vcc) and the collector of the second bipolar transistor, and in another branch of a third bipolar transistor (Q3) configured in emitter follower with a resistor (Rf) in the emitter. The base and the collector of said third bipolar transistor are respectively connected to the common node of said diodes and to said second supply voltage. The resistor is connected to the common node of said first and second transistors to inject the feedback signal (Vf). Because, the two bodies have a low internal resistance and reduce the collector capacitance of the second transistor, the overall bandwidth of the improved amplifier is significantly extended in the very high frequencies (e.g. 20 GHz and above).
    • 公开了一种改进的2级大带宽放大器(20),包括由配置在共发射极中的第一和第二双极晶体管(Q1,Q2)形成的两级,它们与连接到第一电源电压(Gnd )。 输入信号(Vin)经由输入端子(11)施加到所述第一晶体管的基极,而输出信号(Vout)在连接到所述第二晶体管的集电极的输出端子(12)处可用。 提供并行反馈结构(13')。 它包括在第一分支中串联连接在第二电源电压(Vcc)和第二双极晶体管的集电极之间的两个二极管(D1,D2),以及在第三分支中配置的第三双极晶体管 射极跟随器在发射极中具有电阻(Rf)。 所述第三双极晶体管的基极和集电极分别连接到所述二极管的公共节点和所述第二电源电压。 电阻器连接到所述第一和第二晶体管的公共节点以注入反馈信号(Vf)。 因为这两个机体具有较低的内部电阻并且降低了第二晶体管的集电极电容,所以改进的放大器的总带宽在非常高的频率(例如20GHz及以上)中被显着地扩展。
    • 2. 发明授权
    • Differential amplifier with DC offset cancellation
    • 具有直流偏移消除的差分放大器
    • US06914479B1
    • 2005-07-05
    • US10604479
    • 2003-07-24
    • Bertrand GabillardMichel RivierFabrice VoisinPhilippe Girard
    • Bertrand GabillardMichel RivierFabrice VoisinPhilippe Girard
    • H03F3/45
    • H03F3/45475H03F3/45278H03F3/45973H03F2203/45521H03F2203/45652
    • There is disclosed an improved differential amplifier (20) having a feedback loop that generates an amplified output signal (Vout) from an input signal (Vin) supplied by a preceding stage. It comprises an input matching circuit (11) connected to said preceding stage, a buffer (22) and an amplification section (12) connected in series in the direct amplification line, a first amplifier (16), a RC network (17′) and a second amplifier (23) connected in series in a parallel loop between the outputs and the inputs of the amplification section that generate the feedback signal. The role of said buffer and second amplifier associated in a dedicated direct and feedback signal combining block (21) is to respectively isolate the input signal and the feedback signal from the summing nodes (A′,B′) at the amplification section inputs. As a result, the summation of the input signal and the feedback signal is improved, the DC component of the output signal is filtered out in order to significantly reduce the DC offset. In addition, the input impedance matching represented by parameter S11 is considerably improved.
    • 公开了一种具有反馈回路的改进的差分放大器(20),该反馈回路从由前一级提供的输入信号(Vin)产生放大的输出信号(Vout)。 它包括连接到所述前级的输入匹配电路(11),串联连接在直接放大线路中的缓冲器(22)和放大部分(12),第一放大器(16),RC网络(17') 以及在产生反馈信号的输出与放大部分的输入之间并联连接的第二放大器(23)。 在专用直接和反馈信号组合块(21)中相关联的所述缓冲器和第二放大器的作用是在放大部分输入端分别隔离来自求和节点(A',B')的输入信号和反馈信号。 结果,改善了输入信号和反馈信号的总和,输出信号的直流分量被滤除,以便显着减小直流偏移。 此外,由参数S 11表示的输入阻抗匹配得到显着改善。
    • 3. 发明授权
    • Bandgap reference generator utilizing a current trimming circuit
    • 带隙参考发生器利用电流微调电路
    • US07944280B2
    • 2011-05-17
    • US12198183
    • 2008-08-26
    • Bertrand GabillardPhilippe GirardMichel Rivier
    • Bertrand GabillardPhilippe GirardMichel Rivier
    • G05F1/10G05F3/02
    • G05F3/30
    • A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vdd and an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vdd and to a one of the plurality of switches and each switch includes a fuse.
    • 用于提供带隙电压的电路。 该电路包括经典的带隙参考电压产生电路,其包括用作经典带隙基准电路的另一部分的电流镜的第一端第二串联连接的晶体管,并耦合在电源电压Vdd和输出电阻之间。 电路还包括与经典带隙基准产生电路并联耦合的电流微调电路,其包括包括多个晶体管的固定元件部分和包括多个开关的开关部分。 多个晶体管中的每一个耦合到电源电压Vdd和多个开关中的一个,每个开关包括熔丝。
    • 4. 发明申请
    • BANDGAP REFERENCE GENERATOR UTILIZING A CURRENT TRIMMING CIRCUIT
    • 带电参考发生器利用电流调制电路
    • US20090289697A1
    • 2009-11-26
    • US12198183
    • 2008-08-26
    • Bertrand GabillardPhilippe GirardMichel Rivier
    • Bertrand GabillardPhilippe GirardMichel Rivier
    • G05F1/10
    • G05F3/30
    • A circuit for providing a bandgap voltage. The circuit includes a classic bandgap reference voltage generation circuit including first end second serially connected transistors acting as a current mirror to another portion of the classical bandgap reference circuit and being coupled between a supply voltage Vdd and an output resistor. The circuit also includes a current trimming circuit coupled in parallel with the classical bandgap reference generation circuit including a fixed element portion including a plurality of transistors and a switch portion including a plurality of switches. Each of the plurality of transistors is coupled to the supply voltage Vdd and to a one of the plurality of switches and each switch includes a fuse.
    • 用于提供带隙电压的电路。 该电路包括经典的带隙参考电压产生电路,其包括用作电流镜的第一端第二串联连接的晶体管,并经耦合在电源电压Vdd和输出电阻之间。 电路还包括与经典带隙基准产生电路并联耦合的电流微调电路,其包括包括多个晶体管的固定元件部分和包括多个开关的开关部分。 多个晶体管中的每一个耦合到电源电压Vdd和多个开关中的一个,每个开关包括熔丝。
    • 5. 发明授权
    • Circuit for testing a semiconductor chip having embedded arrays
intermixed with logic
    • 用于测试具有与逻辑混合的嵌入式阵列的半导体芯片的电路
    • US5717696A
    • 1998-02-10
    • US391997
    • 1995-02-21
    • Bertrand GabillardMichel Rivier
    • Bertrand GabillardMichel Rivier
    • G01R31/28G01R31/30G11C29/00G11C29/02G11C29/50G11C29/56H01L21/66H05K10/00
    • G11C29/50G01R31/3004
    • A test circuit applicable to chips having embedded arrays intermixed with logic is described. Depending on a control signal, the test circuit connects or isolates the arrays to and from the logic. The test circuit operates as a switch placed between the power supply rail of the logic and the power supply rail of the arrays. All input gates are cross-connected to the power supply rail of the logic, and each output gate is connected to the corresponding power supply rail of the arrays. During TEST mode, the control signal turns off the test circuit, cutting off the arrays. The logic is tested while the memory cells remain unselected. Faulty chips are rejected. When the value of the control signal is inverted, a control gate connects all the power supply rails of the arrays to the power supply rail of the logic. The test sequence for the embedded array is then applied. Faulty memory cells are replaced with repairable ones; otherwise, the faulty chips are rejected. Thus, the manufacturing yield of the mixed chips is improved.
    • 描述了适用于具有与逻辑混合的嵌入式阵列的芯片的测试电路。 根据控制信号,测试电路将阵列与逻辑电路连接或隔离。 测试电路用作逻辑电源轨和阵列的电源轨之间的开关。 所有输入门都与逻辑电源轨交叉连接,每个输出门连接到阵列的相应电源轨。 在TEST模式下,控制信号关闭测试电路,切断阵列。 当存储器单元保持未选择时,该逻辑被测试。 错误的芯片被拒绝。 当控制信号的值反转时,控制栅将阵列的所有电源轨连接到逻辑电源轨。 然后应用嵌入式阵列的测试序列。 故障记忆单元被可修复的单元替换; 否则,故障芯片被拒绝。 因此,混合芯片的制造成品率提高。