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1. 发明授权

US5617426A Clocking mechanism for delay, short path and stuck-at testing 失效
标题翻译：延时，短路和卡住测试的时钟机制
公开(公告)号：US5617426A
公开(公告)日：1997-04-01
申请号：US393511
申请日：1995-02-21
申请人： Bernd K. F. Koenemann , William H. McAnney , Mark L. Shulman
发明人： Bernd K. F. Koenemann , William H. McAnney , Mark L. Shulman
IPC分类号： G01R31/28 , G01R31/3185 , G06F11/22 , H04B17/00
CPC分类号： G01R31/31858 , G01R31/318552
摘要： In a level sensitive scan design (LSSD) circuit embodiment for testing the behavior of logic circuits, a mechanism is provided for generating a skewed load of data into a set of shift register scan string latches. The nature of the input scan string assures that a certain number of 0 to 1 or 1 to 0 transitions occurs as an input to the block of logic being tested. Furthermore, a mechanism for delaying by one system clock cycle time the capture of information from the logic block in a second shift register scan string provides a mechanism for testing for the occurrence of short paths and long paths while preserving testability for stuck-at faults. Furthermore, all of these advantages are achieved without impacting the traditional stuck-fault test capabilities of the level sensitive scan design methodology.
摘要翻译：在用于测试逻辑电路的行为的电平敏感扫描设计（LSSD）电路实施例中，提供了一种机制，用于将数据的偏移负载产生到一组移位寄存器扫描串锁存器中。输入扫描字符串的性质确保了一定数量的0到1或1到0的转换作为被测试逻辑块的输入发生。此外，通过一个系统时钟周期时间延迟在第二移位寄存器扫描串中从逻辑块捕获信息的机制提供了一种用于测试短路径和长路径的发生的机制，同时保持卡住故障的可测试性。此外，所有这些优点都是在不影响级别敏感扫描设计方法的传统卡死故障测试功能的情况下实现的。

2. 发明授权

US4513418A Simultaneous self-testing system 失效
标题翻译：同步自检系统
公开(公告)号：US4513418A
公开(公告)日：1985-04-23
申请号：US440070
申请日：1982-11-08
申请人： Paul H. Bardell, Jr. , William H. McAnney
发明人： Paul H. Bardell, Jr. , William H. McAnney
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , G06F11/00
CPC分类号： G01R31/318547
摘要： The LSSD scan paths on a number of logic circuit chips are modified and connected together in series to simultaneously serve as a random signal generator and data compression circuit to perform random stimuli signature generation.
摘要翻译：多个逻辑电路芯片上的LSSD扫描路径被修改并串联在一起，同时用作随机信号发生器和数据压缩电路，以执行随机刺激签名生成。

3. 发明授权

US5150366A Reduced delay circuits for shift register latch scan strings 失效
标题翻译：用于移位寄存器锁存扫描线的减少延迟电路
公开(公告)号：US5150366A
公开(公告)日：1992-09-22
申请号：US561399
申请日：1990-08-01
申请人： Paul H. Bardell, Jr. , William H. McAnney
发明人： Paul H. Bardell, Jr. , William H. McAnney
IPC分类号： G01R31/28 , G06F11/22 , G06F11/27
CPC分类号： G06F11/27
摘要： Delays in critical signal paths are eliminated in circuits employing level sensitive scan design methods for implementing self-test operations. In particular, scan strings associataed with primary input lines are segregated and supplied to a separate distinct signature register so as to permit simplified degating circuitry on the input side of those shift register latches which are in fact associated with primary input signal lines.

4. 发明授权

US4503537A Parallel path self-testing system 失效
标题翻译：并行路径自检系统
公开(公告)号：US4503537A
公开(公告)日：1985-03-05
申请号：US440065
申请日：1982-11-08
申请人： William H. McAnney
发明人： William H. McAnney
IPC分类号： G01R31/28 , G01R31/317 , G01R31/3185 , G06F11/22 , H01L21/66 , H01L21/822 , H01L27/04 , G06F11/00
CPC分类号： G01R31/318533 , H01L2924/0002
摘要： The LSSD scan paths of each logic circuit chip on a circuit module are connected to additional test circuit chips on the same module. The test chips contain a random signal generator and data compression circuit to perform random stimuli signature generators and also contain switching circuits to connect the scan paths of the chips in parallel between different stages of the random signal generator and the data compression means for random stimuli signature generators and to disconnect the scan paths from the signal generator and data compression circuitry and arrange them serially in a single scan path to perform other tests.
摘要翻译：电路模块上每个逻辑电路芯片的LSSD扫描路径连接到同一模块上的附加测试电路芯片。测试芯片包含随机信号发生器和数据压缩电路，以执行随机刺激特征生成器，并且还包含切换电路，用于将随机信号发生器的不同级之间并行的芯片的扫描路径与用于随机刺激签名的数据压缩装置发生器并断开与信号发生器和数据压缩电路的扫描路径，并将它们串行布置在单个扫描路径中以执行其他测试。

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