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1. 发明授权

US5811987A Block clock and initialization circuit for a complex high density PLD 失效
标题翻译：用于复杂高密度PLD的块时钟和初始化电路
公开(公告)号：US5811987A
公开(公告)日：1998-09-22
申请号：US740948
申请日：1996-11-05
申请人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
发明人： Benjamin Howard Ashmore, Jr. , Jeffery Mark Marshall , Bryon Irwin Moyer , John David Porter , Nicholas A. Schmitz , Bradley A. Sharpe-Geisler
IPC分类号： H03K3/037 , H03K3/356 , H03K19/173 , H03K19/177 , H03K19/21 , H03K7/38
CPC分类号： H03K3/037 , H03K19/1736 , H03K19/17704 , H03K19/17728 , H03K19/1774 , H03K19/17772 , H03K19/215 , H03K3/0375 , H03K3/356156
摘要： A block clock and initialization circuit for a programmable logic block in a complex very high density programmable logic device generates a plurality of block clock signals and block initialization signals for elements in the programmable logic block. The block clock and initialization circuit includes a block clock generator circuit and a block initialization circuit. The block clock generator circuit receives a first set of product terms in a plurality of product terms and a plurality of clock signals as input signals. In response to the input signals, the block clock generator circuit generates output signals on a plurality of block clock lines. The block initialization circuit receives a second set of product terms in the plurality of product terms as input signals. In response to the input signals, the block initialization circuit generates a plurality of output signals on the block initialization lines.
摘要翻译：复合非常高密度可编程逻辑器件中的可编程逻辑块的块时钟和初始化电路为可编程逻辑块中的元件生成多个块时钟信号和块初始化信号。块时钟和初始化电路包括块时钟发生器电路和块初始化电路。块时钟发生器电路以多个乘积项和多个时钟信号作为输入信号接收第一组乘积项。响应于输入信号，块时钟发生器电路在多个块时钟线上产生输出信号。块初始化电路接收多个乘积项中的第二组乘积项作为输入信号。响应于输入信号，块初始化电路在块初始化线上产生多个输出信号。

2. 发明授权

US06753696B1 Programmable optimized-distribution logic allocator for a high-density complex PLD 失效
标题翻译：用于高密度复合PLD的可编程优化分配逻辑分配器
公开(公告)号：US06753696B1
公开(公告)日：2004-06-22
申请号：US10338619
申请日：2003-01-08
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz
IPC分类号： H03K19173
CPC分类号： H03K19/177 , H03K19/1737 , H03K19/17704
摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.
摘要翻译：可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到可编程选择逻辑宏单元。具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。

3. 发明授权

US5521529A Very high-density complex programmable logic devices with a multi-tiered hierarchical switch matrix and optimized flexible logic allocation 失效
标题翻译：具有多层分层交换矩阵和优化的灵活逻辑分配的非常高密度的复杂可编程逻辑器件
公开(公告)号：US5521529A
公开(公告)日：1996-05-28
申请号：US459960
申请日：1995-06-02
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz , Bryon I. Moyer
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz , Bryon I. Moyer
IPC分类号： H03K19/177 , H03K19/082 , H03K19/173
CPC分类号： H03K19/17736 , H03K19/17704
摘要： A very high-density complex programmable logic device (CPLD) has a plurality of hierarchical signal paths. The lowest level of the hierarchy is independent from all higher levels. Similarly, an intermediate level is independent from all higher levels and utilizes only resources of the CPLD associated with the lowest and intermediate hierarchical levels. The first hierarchical level resources include a programmable logic block having a plurality of input lines and a plurality of output lines, and a programmable block switch matrix connected to the plurality of input lines of the programmable logic block. The second hierarchical level resources include a programmable segment switch matrix connected to a plurality of input lines of the programmable block switch matrix. The CPLD in addition includes a third hierarchical level circuit having third hierarchial level resources connected to the second hierarchical level resources where a third hierarchical level signal path utilizes the third, second, and first hierarchical level resources. The third hierarchical level resources include a programmable global switch matrix having global switch matrix lines programmably connected to and disconnected from lines of the programmable segment switch matrix.
摘要翻译：一种非常高密度的复杂可编程逻辑器件（CPLD）具有多个层级信号路径。层次结构的最低层次与所有更高层次是独立的。类似地，中间级别与所有较高级别无关，并且仅利用与最低和中级层级相关联的CPLD的资源。第一层级资源包括具有多个输入线和多条输出线的可编程逻辑块以及连接到可编程逻辑块的多条输入线的可编程块开关矩阵。第二层级资源包括连接到可编程块开关矩阵的多个输入线的可编程段开关矩阵。 CPLD另外包括具有连接到第二层级资源的第三层级资源的第三层级电路，其中第三级别信号路径利用第三级，第二级和第一层次级资源。第三层级资源包括可编程全局开关矩阵，其具有可编程地连接到可编程段开关矩阵的线路并与其断开的全局开关矩阵线。

4. 发明授权

US06531890B1 Programmable optimized-distribution logic allocator for a high-density complex PLD 失效
标题翻译：用于高密度复合PLD的可编程优化分配逻辑分配器
公开(公告)号：US06531890B1
公开(公告)日：2003-03-11
申请号：US08459570
申请日：1995-06-02
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler , Nicholas A. Schmitz
IPC分类号： H03K19177
CPC分类号： H03K19/177 , H03K19/1737 , H03K19/17704
摘要： A programmable optimized-distribution logic allocator enhances the speed, silicon utilization, logic efficiency, logic utilization, and scalability of very high-density CPLDs including the logic allocator. The programmable optimized-distribution logic allocator provides an optimized number of product terms to each I/O pin of the CPLDS and the same uniform number of product terms as feedback. However, no product terms are permanently connected to either a particular macrocell or a particular I/O pin. The programmable optimized-distribution logic allocator includes a multiplicity of router elements where each router element steers a sum of a selected number of sum-of-product terms from a PAL structure, i.e, a selected number of logic product-term clusters, to a programmably selected logic macrocell. Specifically, the programmable optimized-distribution logic allocator has a plurality of input lines, a plurality of output lines and a plurality of programmable router elements. Each programmable router element has an input terminal connected an input line in the plurality of input lines and an output terminal connected to an output line in the plurality of output lines.
摘要翻译：可编程优化分配逻辑分配器增强了包括逻辑分配器在内的非常高密度CPLD的速度，硅利用率，逻辑效率，逻辑利用率和可扩展性。可编程优化分配逻辑分配器为CPLDS的每个I / O引脚提供优化数量的产品术语，并且与反馈相同的统一数量的产品术语。然而，没有产品术语永久连接到特定的宏单元或特定的I / O引脚。可编程优化分配逻辑分配器包括多个路由器元件，其中每个路由器元件将选择数量的乘积项和项的总和从PAL结构（即选定数量的逻辑产品项集群）引导到可编程选择逻辑宏单元。具体地，可编程优化分配逻辑分配器具有多条输入线，多条输出线和多条可编程路由器元件。每个可编程路由器元件具有连接多条输入线中的输入线的输入端和连接到多条输出行中的输出线的输出端。

5. 发明授权

US07028281B1 FPGA with register-intensive architecture 有权
标题翻译：具有寄存器密集型架构的FPGA
公开(公告)号：US07028281B1
公开(公告)日：2006-04-11
申请号：US10194771
申请日：2002-07-12
申请人： Om P. Agrawal , Bradley A. Sharpe-Geisler
发明人： Om P. Agrawal , Bradley A. Sharpe-Geisler
IPC分类号： G06F17/50
CPC分类号： H03K19/17736 , G06F17/5054 , H01L2924/0002 , H03K19/17728 , H03K19/17784 , H01L2924/00
摘要： Field programmable gate arrays (FPGA's) may be structured in accordance with the disclosure to have a register-intensive architecture that provides, for each of plural function-spawning LookUp Tables (e.g. a 4-input, base LUT's) within a logic block, a plurality of in-block accessible registers. A register-feeding multiplexer means may be provided for allowing each of the plural registers to equivalently capture and store a result signal output by the corresponding, base LUT of the plural registers. Registerable, primary and secondary feedthroughs may be provided for each base LUT so that locally-acquired input signals of the LUT may be fed-through to the corresponding, in-block registers for register-recovery purposes without fully consuming (wasting) the lookup resources of the associated, base LUT. A multi-stage, input switch matrix (ISM) may be further provided for acquiring and routing input signals from adjacent, block-interconnect lines (AIL's) and/or block-intra-connect lines (e.g., FB's) to the base LUT's and/or their respective, registerable feedthroughs. Techniques are disclosed for utilizing the many in-block registers and/or the registerable feedthroughs and/or the multi-stage ISM's for efficiently implementing various circuit designs by appropriately configuring such register-intensive FPGA's.
摘要翻译：现场可编程门阵列（FPGA）可以根据本公开进行结构化以具有寄存器密集型架构，其针对逻辑块内的多个功能产生查找表（例如，4输入，基本LUT）中的每一个提供寄存器密集型结构，多个块内可访问寄存器。可以提供寄存器馈送多路复用器装置，用于允许多个寄存器中的每一个等效地捕获并存储由多个寄存器的相应的基本LUT输出的结果信号。可以为每个基本LUT提供可登记的主和辅助馈通，使得LUT的本地采集的输入信号可以被馈送到相应的块内寄存器用于寄存器恢复目的，而不会完全消耗（浪费）查找资源的相关的基本LUT。可以进一步提供多级输入开关矩阵（ISM），用于从相邻的块互连线（AIL）和/或块内连接线（例如，FB）到基本LUT的采集和路由输入信号，并且 /或其各自的可注册馈通。公开了利用许多块内寄存器和/或可注册馈通和/或多级ISM的技术来通过适当地配置这种寄存器密集型FPGA来有效地实现各种电路设计。

6. 发明授权

US06870391B1 Input buffer with CMOS driver gate current control enabling selectable PCL, GTL, or PECL compatibility 有权
标题翻译：具有CMOS驱动器门电流控制的输入缓冲器，可实现PCL，GTL或PECL的兼容性
公开(公告)号：US06870391B1
公开(公告)日：2005-03-22
申请号：US10146769
申请日：2002-05-16
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： G06F7/38 , H03K19/0185
CPC分类号： H03K19/018521 , H03K19/018585
摘要： An input/output buffer is provided which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. The input buffer portion includes a first pair of CMOS transistors for driving the output (OUT) between the VSS and VDD rails similar to CMOS logic. Switching circuitry includes transistors which drive gates of the CMOS transistors to set the output (OUT) with a current level and a voltage level depending on a desired output drive current and voltage.
摘要翻译：提供了一种输入/输出缓冲器，可用于使集成电路选择性地兼容多种接口类型之一，如PCI，GTL，PECL，ECL和SSTI。输入缓冲器部分包括第一对CMOS晶体管，用于驱动类似于CMOS逻辑的VSS和VDD电压之间的输出（OUT）。开关电路包括驱动CMOS晶体管的栅极的晶体管，以根据期望的输出驱动电流和电压将电流电平和电压电平设置为输出（OUT）。

7. 发明授权

US06798244B1 Output buffer with overvoltage protection 失效
标题翻译：输出缓冲器，具有过压保护功能
公开(公告)号：US06798244B1
公开(公告)日：2004-09-28
申请号：US10151753
申请日：2002-05-16
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K190175
CPC分类号： H03K19/018585 , H03K17/163
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The input buffer includes switching circuitry driving the gates of multiple CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. The switching circuitry includes components to prevent damage to low voltage transistors used in the output buffer should the output pad (PAD) voltage exceed VDD, or should charge buildup occur on the common well of PMOS transistors used in the output buffer exceed VDD.
摘要翻译：输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。输入缓冲器包括驱动多个CMOS缓冲晶体管的栅极的开关电路，以提供足够的电流用于快速开关，并且在切换之后限制电流以准备随后的输出转换。如果输出缓冲器（PAD）电压超过VDD，或者在输出缓冲器中使用的PMOS晶体管的公共阱上的电荷积累超过VDD，则开关电路包括防止损坏输出缓冲器中使用的低压晶体管的组件。

8. 发明授权

US06657458B1 Output buffer with feedback from an input buffer to provide selectable PCL, GTL, or PECL compatibility 失效
标题翻译：输出缓冲器，具有来自输入缓冲器的反馈，提供可选择的PCL，GTL或PECL兼容性
公开(公告)号：US06657458B1
公开(公告)日：2003-12-02
申请号：US10146826
申请日：2002-05-16
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： H03K19177
CPC分类号： H03K19/018585
摘要： An input/output buffer is provided with an output buffer portion which can be used to make an integrated circuit selectively compatible with one of a number of interface types, such as PCI, GTL, PECL, ECL and SSTI. An output buffer portion has an input for receiving an output signal node (D) where components on the integrated circuit provide an output signal for connecting to external circuits at an output pad (PAD). The signal from the PAD is further fed back through the input buffer portion which programmably set to operate in a PCI, PECL or GTL mode to control a node (INB). The node (INB) is used to control power switches driving the gates of CMOS buffer transistors to provide sufficient current for rapid switching, and limit current after switching to prepare for a subsequent output transition. Pull-up and pull-down reference circuits provide references VRFPU, VRFPPU, VRFPD and VRFPPD to control the current of the output during transition of the output, while maintaining the output voltage level at a desired voltage with minimal current level after transition.
摘要翻译：输入/输出缓冲器具有输出缓冲器部分，其可用于使集成电路选择性地与诸如PCI，GTL，PECL，ECL和SSTI之类的接口类型之一兼容。输出缓冲器部分具有用于接收输出信号节点（D）的输入，其中集成电路上的组件提供用于在输出焊盘（PAD）处连接到外部电路的输出信号。来自PAD的信号通过可编程设置为以PCI，PECL或GTL模式操作以控制节点（INB）的输入缓冲器部分进一步反馈。节点（INB）用于控制驱动CMOS缓冲晶体管的栅极的电源开关，以提供足够的电流用于快速开关，并在切换后限制电流以准备后续的输出转换。上拉和下拉参考电路提供参考VRFPU，VRFPPU，VRFPD和VRFPPD，以在输出转换期间控制输出电流，同时在转换后以最小的电流水平将输出电压电平保持在所需电压。

9. 发明授权

US06181163B2 FPGA integrated circuit having embedded SRAM memory blocks and interconnect channel for broadcasting address and control signals 有权
标题翻译： FPGA集成电路具有嵌入式SRAM存储块和用于广播地址和控制信号的互连通道
公开(公告)号：US06181163B2
公开(公告)日：2001-01-30
申请号：US09235351
申请日：1999-01-21
申请人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
发明人： Om P. Agrawal , Herman M. Chang , Bradley A. Sharpe-Geisler , Bai Nguyen
IPC分类号： H03K19177
CPC分类号： H03K19/1776 , H03K19/17736
摘要： A field-programmable gate array device (FPGA) having plural rows and columns of logic function units (VGB's) further includes a plurality of embedded memory blocks, where each memory block is embedded in a corresponding row of logic function units. Each embedded memory block has an address port for capturing received address signals and a controls port for capturing supplied control signals. Interconnect resources are provided including a Memory Controls-conveying Interconnect Channel (MCIC) for conveying shared address and control signals to plural ones of the memory blocks on a broadcast or narrowcast basis.
摘要翻译：具有多个行和列的逻辑功能单元（VGB）的现场可编程门阵列器件（FPGA）还包括多个嵌入式存储器块，其中每个存储器块被嵌入相应的逻辑功能单元行中。每个嵌入式存储块具有用于捕获接收的地址信号的地址端口和用于捕获所提供的控制信号的控制端口。提供互连资源，包括用于以广播或窄播为基础将共享地址和控制信号传送到多个存储器块的存储器控制传送互连信道（MCIC）。

10. 发明授权

US06175266B1 Operational amplifier with CMOS transistors made using 2.5 volt process transistors 有权
标题翻译：具有采用2.5伏过程晶体管的CMOS晶体管的运算放大器
公开(公告)号：US06175266B1
公开(公告)日：2001-01-16
申请号：US09207558
申请日：1998-12-08
申请人： Bradley A. Sharpe-Geisler
发明人： Bradley A. Sharpe-Geisler
IPC分类号： G05F302
CPC分类号： G05F1/575
摘要： A power converter includes an opamp (FIG. 5) with CMOS transistors made using 2.5 volt process technology which tolerates a maximum gate voltage of 2.7 volts. The opamp is driven by a pin supply voltage (NV3EXT) with a maximum value of 3.6 volts. The connection of the transistors of the opamp (FIG. 5) provides a maximum gate to source, and gate to drain voltage on each transistor which is less than 2.7 volts when NV3EXT is at 3.6 volts. Further, the output (OUT) of the opamp (FIG. 5) is referenced to ground, rather than NV3EXT to prevent fluctuations in the input voltage offset relative to NV3EXT, and minimize variations in the output voltage margin of the power converter.
摘要翻译：功率转换器包括具有使用2.5伏工艺技术制造的CMOS晶体管的运算放大器（图5），其允许2.7V的最大栅极电压。运算放大器由最大值为3.6伏特的引脚电源电压（NV3EXT）驱动。当NV3EXT为3.6伏时，运算放大器（图5）的晶体管的连接提供了每个晶体管上的最大栅极至源极以及小于2.7伏特的栅极至漏极电压。此外，运算放大器（图5）的输出（OUT）参考地，而不是NV3EXT，以防止相对于NV3EXT的输入电压偏移的波动，并使功率转换器的输出电压余量的变化最小化。

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